Searched refs:HW_SSP_CTRL0 (Results 1 – 3 of 3) sorted by relevance
90 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer()191 ctrl0 = readl(ssp->base + HW_SSP_CTRL0); in mxs_spi_txrx_dma()305 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()310 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()314 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()316 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()329 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()331 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1)) in mxs_spi_txrx_pio()[all …]
19 #define HW_SSP_CTRL0 0x000 macro
115 writel(ctrl0, ssp->base + HW_SSP_CTRL0); in mxs_mmc_reset()521 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()526 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_mmc_enable_sdio_irq()
