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Searched refs:HHI_VIID_CLK_CNTL (Results 1 – 9 of 9) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/meson/
Dmeson_vclk.c60 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
293 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); in meson_venci_cvbs_clock_config()
304 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
307 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
311 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); in meson_venci_cvbs_clock_config()
325 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
329 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
331 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
/Linux-v6.6/drivers/clk/meson/
Dmeson8b.h28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
Daxg.h52 #define HHI_VIID_CLK_CNTL 0x12c macro
Dgxbb.h34 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
Dg12a.h55 #define HHI_VIID_CLK_CNTL 0x12C macro
Daxg.c1316 .offset = HHI_VIID_CLK_CNTL,
1407 .offset = HHI_VIID_CLK_CNTL,
1491 .offset = HHI_VIID_CLK_CNTL,
1505 .offset = HHI_VIID_CLK_CNTL,
1519 .offset = HHI_VIID_CLK_CNTL,
1533 .offset = HHI_VIID_CLK_CNTL,
1547 .offset = HHI_VIID_CLK_CNTL,
Dgxbb.c1888 .offset = HHI_VIID_CLK_CNTL,
1984 .offset = HHI_VIID_CLK_CNTL,
2068 .offset = HHI_VIID_CLK_CNTL,
2082 .offset = HHI_VIID_CLK_CNTL,
2096 .offset = HHI_VIID_CLK_CNTL,
2110 .offset = HHI_VIID_CLK_CNTL,
2124 .offset = HHI_VIID_CLK_CNTL,
Dg12a.c3159 .offset = HHI_VIID_CLK_CNTL,
3250 .offset = HHI_VIID_CLK_CNTL,
3334 .offset = HHI_VIID_CLK_CNTL,
3348 .offset = HHI_VIID_CLK_CNTL,
3362 .offset = HHI_VIID_CLK_CNTL,
3376 .offset = HHI_VIID_CLK_CNTL,
3390 .offset = HHI_VIID_CLK_CNTL,
Dmeson8b.c1424 .offset = HHI_VIID_CLK_CNTL,