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Searched refs:HCLK (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.6/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
/Linux-v6.6/Documentation/devicetree/bindings/clock/
Dst,nomadik.txt34 HCLK nodes: these represent the clock gates on individual
35 lines from the HCLK clock tree and the gate for individual
38 Requires properties for the HCLK nodes:
/Linux-v6.6/include/video/
Dkyro.h33 u32 HCLK; /* Hor Clock */ member
/Linux-v6.6/include/dt-bindings/clock/
Dsamsung,s3c64xx-clock.h27 #define HCLK 8 macro
Dstm32h7-clks.h3 #define HCLK 1 macro
/Linux-v6.6/drivers/mmc/host/
Dtoshsd.c86 while (ios->clock < HCLK / div) in __toshsd_set_ios()
642 mmc->f_min = HCLK / 512; in toshsd_probe()
643 mmc->f_max = HCLK; in toshsd_probe()
Dtoshsd.h11 #define HCLK 33000000 /* 33 MHz (PCI clock) */ macro
/Linux-v6.6/drivers/clk/samsung/
Dclk-s3c64xx.c163 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
317 ALIAS(HCLK, NULL, "hclk"),
/Linux-v6.6/arch/arm/boot/dts/st/
Dste-nomadik-stn8815.dtsi226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
232 /* The PCLK domain uses HCLK right off */
/Linux-v6.6/drivers/video/fbdev/kyro/
Dfbdev.c509 par->HCLK = (1000000000 + (lineclock / 2)) / lineclock; in kyrofb_set_par()
/Linux-v6.6/drivers/clk/nxp/
Dclk-lpc32xx.c213 LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
1249 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
/Linux-v6.6/drivers/clk/
Dclk-stm32h7.c517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", in register_core_and_bus_clocks()