Searched refs:HAS_PCH_SPLIT (Results 1 – 23 of 23) sorted by relevance
245 if (HAS_PCH_SPLIT(i915)) { in intel_pre_enable_lvds()456 if (HAS_PCH_SPLIT(i915)) in intel_lvds_compute_config()855 if (HAS_PCH_SPLIT(i915)) in intel_lvds_init()862 if (HAS_PCH_SPLIT(i915)) { in intel_lvds_init()900 if (HAS_PCH_SPLIT(i915)) { in intel_lvds_init()
38 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) in intel_hdmi_prepare()136 if (HAS_PCH_SPLIT(i915)) in g4x_hdmi_compute_config()183 if (!HAS_PCH_SPLIT(dev_priv) && in intel_hdmi_get_config()721 if (HAS_PCH_SPLIT(dev_priv)) { in g4x_hdmi_init()
194 if (!HAS_PCH_SPLIT(dev_priv)) in intel_crt_set_dpms()469 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); in ilk_crt_detect_hotplug()572 if (HAS_PCH_SPLIT(dev_priv)) in intel_crt_detect_hotplug()999 if (HAS_PCH_SPLIT(dev_priv)) in intel_crt_init()1084 if (HAS_PCH_SPLIT(dev_priv)) { in intel_crt_init()
741 } else if (HAS_PCH_SPLIT(dev_priv)) { in intel_dp_aux_init()753 else if (HAS_PCH_SPLIT(dev_priv)) in intel_dp_aux_init()
66 } else if (HAS_PCH_SPLIT(dev_priv)) { in g4x_dp_set_clock()1341 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { in g4x_dp_init()
222 if (HAS_PCH_SPLIT(dev_priv)) { in intel_sdvo_write_sdvox()1360 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) in intel_sdvo_compute_config()3318 if (HAS_PCH_SPLIT(dev_priv)) in is_sdvo_port_valid()3378 if (HAS_PCH_SPLIT(dev_priv)) { in intel_sdvo_init()
1119 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && in gen8_de_irq_handler()1651 else if (HAS_PCH_SPLIT(dev_priv)) in gen8_de_irq_postinstall()
1666 if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915)) in intel_pps_setup()1684 if (HAS_PCH_SPLIT(dev_priv)) { in assert_pps_unlocked()
937 if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { in intel_display_device_info_runtime_init()
163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) in intel_hpd_init_pins()
976 else if (HAS_PCH_SPLIT(dev_priv)) in intel_hdmi_set_gcp_infoframe()1001 else if (HAS_PCH_SPLIT(dev_priv)) in intel_hdmi_read_gcp_infoframe()
65 else if (HAS_PCH_SPLIT(dev_priv)) in i915_sr_status()
861 if (!HAS_PCH_SPLIT(dev_priv)) in bxt_enable_dc9()
3826 else if (HAS_PCH_SPLIT(dev_priv)) in i9xx_pll_refclk()6466 } else if (HAS_PCH_SPLIT(dev_priv)) { in intel_pipe_fastset()7422 } else if (HAS_PCH_SPLIT(dev_priv)) { in intel_setup_outputs()7775 } else if (HAS_PCH_SPLIT(dev_priv)) { in intel_init_display_hooks()
1557 else if (HAS_PCH_SPLIT(dev_priv)) in intel_dpll_init_clock_hook()
1805 } else if (HAS_PCH_SPLIT(i915)) { in intel_backlight_init_funcs()
2787 !HAS_PCH_SPLIT(i915)); in init_vbt_defaults()
3379 else if (HAS_PCH_SPLIT(dev_priv)) in intel_read_rawclk()
4009 if (HAS_PCH_SPLIT(dev_priv)) { in i9xx_wm_init()
2264 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) in intel_dp_compute_config()
87 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) macro
720 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_reset()
1767 else if (HAS_PCH_SPLIT(i915)) in gt_record_display_regs()1808 } else if (HAS_PCH_SPLIT(i915)) { in gt_record_global_nonguc_regs()