1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023, Linaro Ltd.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/soundwire/sdw.h>
18 #include <linux/soundwire/sdw_registers.h>
19 #include <linux/soundwire/sdw_type.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc-dapm.h>
23 #include <sound/soc.h>
24 #include <sound/tlv.h>
25
26 #define WSA884X_BASE 0x3000
27 #define WSA884X_ANA_BG_TSADC_BASE (WSA884X_BASE + 0x0001)
28 #define WSA884X_BG_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x00)
29 #define WSA884X_ADC_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x01)
30 #define WSA884X_BOP1_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x02)
31 #define WSA884X_BOP2_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x03)
32 #define WSA884X_BOP2_PROG_BOP2_VTH_MASK 0xf0
33 #define WSA884X_BOP2_PROG_BOP2_VTH_SHIFT 4
34 #define WSA884X_BOP2_PROG_BOP2_HYST_MASK 0x0f
35 #define WSA884X_BOP2_PROG_BOP2_HYST_SHIFT 0
36 #define WSA884X_UVLO_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x04)
37 #define WSA884X_UVLO_PROG1 (WSA884X_ANA_BG_TSADC_BASE + 0x05)
38 #define WSA884X_SPARE_CTRL_0 (WSA884X_ANA_BG_TSADC_BASE + 0x06)
39 #define WSA884X_SPARE_CTRL_1 (WSA884X_ANA_BG_TSADC_BASE + 0x07)
40 #define WSA884X_SPARE_CTRL_2 (WSA884X_ANA_BG_TSADC_BASE + 0x08)
41 #define WSA884X_SPARE_CTRL_3 (WSA884X_ANA_BG_TSADC_BASE + 0x09)
42 #define WSA884X_REF_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x0a)
43 #define WSA884X_REF_CTRL_BG_RDY_SEL_MASK 0x03
44 #define WSA884X_REF_CTRL_BG_RDY_SEL_SHIFT 0
45 #define WSA884X_BG_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0b)
46 #define WSA884X_BG_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x0c)
47 #define WSA884X_ADC_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x0d)
48 #define WSA884X_ADC_IREF_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0e)
49 #define WSA884X_ADC_ISENS_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0f)
50 #define WSA884X_ADC_CLK_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x10)
51 #define WSA884X_ADC_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x11)
52 #define WSA884X_ADC_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x12)
53 #define WSA884X_VBAT_SNS (WSA884X_ANA_BG_TSADC_BASE + 0x13)
54 #define WSA884X_DOUT_MSB (WSA884X_ANA_BG_TSADC_BASE + 0x14)
55 #define WSA884X_DOUT_LSB (WSA884X_ANA_BG_TSADC_BASE + 0x15)
56 #define WSA884X_BOP_ATEST_SEL (WSA884X_ANA_BG_TSADC_BASE + 0x16)
57 #define WSA884X_MISC0 (WSA884X_ANA_BG_TSADC_BASE + 0x17)
58 #define WSA884X_MISC1 (WSA884X_ANA_BG_TSADC_BASE + 0x18)
59 #define WSA884X_MISC2 (WSA884X_ANA_BG_TSADC_BASE + 0x19)
60 #define WSA884X_MISC3 (WSA884X_ANA_BG_TSADC_BASE + 0x1a)
61 #define WSA884X_SPARE_TSBG_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1b)
62 #define WSA884X_SPARE_TUNE_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1c)
63 #define WSA884X_SPARE_TUNE_1 (WSA884X_ANA_BG_TSADC_BASE + 0x1d)
64
65 #define WSA884X_ANA_IVSENSE_BASE (WSA884X_BASE + 0x0020)
66 #define WSA884X_VSENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x00)
67 #define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK 0xe0
68 #define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 5
69 #define WSA884X_ISENSE2 (WSA884X_ANA_IVSENSE_BASE + 0x01)
70 #define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0
71 #define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 5
72
73 #define WSA884X_SPARE_CTL_1 (WSA884X_ANA_IVSENSE_BASE + 0x02)
74 #define WSA884X_SPARE_CTL_2 (WSA884X_ANA_IVSENSE_BASE + 0x03)
75 #define WSA884X_SPARE_CTL_3 (WSA884X_ANA_IVSENSE_BASE + 0x04)
76 #define WSA884X_SPARE_CTL_4 (WSA884X_ANA_IVSENSE_BASE + 0x05)
77 #define WSA884X_EN (WSA884X_ANA_IVSENSE_BASE + 0x06)
78 #define WSA884X_OVERRIDE1 (WSA884X_ANA_IVSENSE_BASE + 0x07)
79 #define WSA884X_OVERRIDE2 (WSA884X_ANA_IVSENSE_BASE + 0x08)
80 #define WSA884X_ISENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x09)
81 #define WSA884X_ISENSE_CAL (WSA884X_ANA_IVSENSE_BASE + 0x0a)
82 #define WSA884X_MISC (WSA884X_ANA_IVSENSE_BASE + 0x0b)
83 #define WSA884X_ADC_0 (WSA884X_ANA_IVSENSE_BASE + 0x0c)
84 #define WSA884X_ADC_1 (WSA884X_ANA_IVSENSE_BASE + 0x0d)
85 #define WSA884X_ADC_2 (WSA884X_ANA_IVSENSE_BASE + 0x0e)
86 #define WSA884X_ADC_3 (WSA884X_ANA_IVSENSE_BASE + 0x0f)
87 #define WSA884X_ADC_4 (WSA884X_ANA_IVSENSE_BASE + 0x10)
88 #define WSA884X_ADC_5 (WSA884X_ANA_IVSENSE_BASE + 0x11)
89 #define WSA884X_ADC_6 (WSA884X_ANA_IVSENSE_BASE + 0x12)
90 #define WSA884X_ADC_7 (WSA884X_ANA_IVSENSE_BASE + 0x13)
91 #define WSA884X_STATUS (WSA884X_ANA_IVSENSE_BASE + 0x14)
92 #define WSA884X_IVSENSE_SPARE_TUNE_1 (WSA884X_ANA_IVSENSE_BASE + 0x15)
93 #define WSA884X_SPARE_TUNE_2 (WSA884X_ANA_IVSENSE_BASE + 0x16)
94 #define WSA884X_SPARE_TUNE_3 (WSA884X_ANA_IVSENSE_BASE + 0x17)
95 #define WSA884X_SPARE_TUNE_4 (WSA884X_ANA_IVSENSE_BASE + 0x18)
96
97 #define WSA884X_ANA_SPK_TOP_BASE (WSA884X_BASE + 0x0040)
98 #define WSA884X_TOP_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x00)
99 #define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK 0x01
100 #define WSA884X_CLIP_DET_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x01)
101 #define WSA884X_CLIP_DET_CTRL2 (WSA884X_ANA_SPK_TOP_BASE + 0x02)
102 #define WSA884X_DAC_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x03)
103 #define WSA884X_DAC_VCM_CTRL_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x04)
104 #define WSA884X_DAC_VCM_CTRL_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x05)
105 #define WSA884X_DAC_VCM_CTRL_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x06)
106 #define WSA884X_DAC_VCM_CTRL_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x07)
107 #define WSA884X_DAC_VCM_CTRL_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x08)
108 #define WSA884X_DAC_VCM_CTRL_REG6 (WSA884X_ANA_SPK_TOP_BASE + 0x09)
109 #define WSA884X_PWM_CLK_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0a)
110 #define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_MASK 0x80
111 #define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_SHIFT 7
112 #define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_MASK 0x40
113 #define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_SHIFT 6
114 #define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_MASK 0x30
115 #define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_SHIFT 4
116 #define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK 0x08
117 #define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_SHIFT 3
118 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_MASK 0x06
119 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_SHIFT 1
120 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_MASK 0x01
121 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_SHIFT 0
122 #define WSA884X_DRV_LF_LDO_SEL (WSA884X_ANA_SPK_TOP_BASE + 0x0b)
123 #define WSA884X_OCP_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0c)
124 #define WSA884X_PDRV_HS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0d)
125 #define WSA884X_PDRV_LS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0e)
126 #define WSA884X_SPK_TOP_SPARE_CTL_1 (WSA884X_ANA_SPK_TOP_BASE + 0x0f)
127 #define WSA884X_SPK_TOP_SPARE_CTL_2 (WSA884X_ANA_SPK_TOP_BASE + 0x10)
128 #define WSA884X_SPK_TOP_SPARE_CTL_3 (WSA884X_ANA_SPK_TOP_BASE + 0x11)
129 #define WSA884X_SPK_TOP_SPARE_CTL_4 (WSA884X_ANA_SPK_TOP_BASE + 0x12)
130 #define WSA884X_SPARE_CTL_5 (WSA884X_ANA_SPK_TOP_BASE + 0x13)
131 #define WSA884X_DAC_EN_DEBUG_REG (WSA884X_ANA_SPK_TOP_BASE + 0x14)
132 #define WSA884X_DAC_OPAMP_BIAS1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x15)
133 #define WSA884X_DAC_OPAMP_BIAS2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x16)
134 #define WSA884X_DAC_TUNE1 (WSA884X_ANA_SPK_TOP_BASE + 0x17)
135 #define WSA884X_DAC_VOLTAGE_CTRL_REG (WSA884X_ANA_SPK_TOP_BASE + 0x18)
136 #define WSA884X_ATEST1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x19)
137 #define WSA884X_ATEST2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x1a)
138 #define WSA884X_TOP_BIAS_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x1b)
139 #define WSA884X_TOP_BIAS_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1c)
140 #define WSA884X_TOP_BIAS_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x1d)
141 #define WSA884X_TOP_BIAS_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x1e)
142 #define WSA884X_PWRSTG_DBG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1f)
143 #define WSA884X_DRV_LF_BLK_EN (WSA884X_ANA_SPK_TOP_BASE + 0x20)
144 #define WSA884X_DRV_LF_EN (WSA884X_ANA_SPK_TOP_BASE + 0x21)
145 #define WSA884X_DRV_LF_MASK_DCC_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x22)
146 #define WSA884X_DRV_LF_MISC_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x23)
147 #define WSA884X_DRV_LF_REG_GAIN (WSA884X_ANA_SPK_TOP_BASE + 0x24)
148 #define WSA884X_DRV_OS_CAL_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x25)
149 #define WSA884X_DRV_OS_CAL_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x26)
150 #define WSA884X_PWRSTG_DBG (WSA884X_ANA_SPK_TOP_BASE + 0x27)
151 #define WSA884X_BBM_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x28)
152 #define WSA884X_TOP_MISC1 (WSA884X_ANA_SPK_TOP_BASE + 0x29)
153 #define WSA884X_DAC_VCM_CTRL_REG7 (WSA884X_ANA_SPK_TOP_BASE + 0x2a)
154 #define WSA884X_TOP_BIAS_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x2b)
155 #define WSA884X_DRV_LF_MISC_CTL2 (WSA884X_ANA_SPK_TOP_BASE + 0x2c)
156 #define WSA884X_SPK_TOP_SPARE_TUNE_2 (WSA884X_ANA_SPK_TOP_BASE + 0x2d)
157 #define WSA884X_SPK_TOP_SPARE_TUNE_3 (WSA884X_ANA_SPK_TOP_BASE + 0x2e)
158 #define WSA884X_SPK_TOP_SPARE_TUNE_4 (WSA884X_ANA_SPK_TOP_BASE + 0x2f)
159 #define WSA884X_SPARE_TUNE_5 (WSA884X_ANA_SPK_TOP_BASE + 0x30)
160 #define WSA884X_SPARE_TUNE_6 (WSA884X_ANA_SPK_TOP_BASE + 0x31)
161 #define WSA884X_SPARE_TUNE_7 (WSA884X_ANA_SPK_TOP_BASE + 0x32)
162 #define WSA884X_SPARE_TUNE_8 (WSA884X_ANA_SPK_TOP_BASE + 0x33)
163 #define WSA884X_SPARE_TUNE_9 (WSA884X_ANA_SPK_TOP_BASE + 0x34)
164 #define WSA884X_SPARE_TUNE_10 (WSA884X_ANA_SPK_TOP_BASE + 0x35)
165 #define WSA884X_PA_STATUS0 (WSA884X_ANA_SPK_TOP_BASE + 0x36)
166 #define WSA884X_PA_STATUS1 (WSA884X_ANA_SPK_TOP_BASE + 0x37)
167 #define WSA884X_PA_STATUS2 (WSA884X_ANA_SPK_TOP_BASE + 0x38)
168 #define WSA884X_PA_STATUS3 (WSA884X_ANA_SPK_TOP_BASE + 0x39)
169 #define WSA884X_PA_STATUS4 (WSA884X_ANA_SPK_TOP_BASE + 0x3a)
170 #define WSA884X_PA_STATUS5 (WSA884X_ANA_SPK_TOP_BASE + 0x3b)
171 #define WSA884X_SPARE_RO_1 (WSA884X_ANA_SPK_TOP_BASE + 0x3c)
172 #define WSA884X_SPARE_RO_2 (WSA884X_ANA_SPK_TOP_BASE + 0x3d)
173 #define WSA884X_SPARE_RO_3 (WSA884X_ANA_SPK_TOP_BASE + 0x3e)
174
175 #define WSA884X_ANA_BOOST_BASE (WSA884X_BASE + 0x0090)
176 #define WSA884X_STB_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x00)
177 #define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK 0xf8
178 #define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_SHIFT 3
179 #define WSA884X_STB_CTRL1_VOUT_FS_MASK 0x07
180 #define WSA884X_STB_CTRL1_VOUT_FS_SHIFT 0
181 #define WSA884X_CURRENT_LIMIT (WSA884X_ANA_BOOST_BASE + 0x01)
182 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80
183 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 7
184 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c
185 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 2
186 #define WSA884X_CURRENT_LIMIT_CLK_PHASE_SHIFT 0
187 #define WSA884X_BYP_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x02)
188 #define WSA884X_SPARE_CTL_0 (WSA884X_ANA_BOOST_BASE + 0x03)
189 #define WSA884X_BOOST_SPARE_CTL_1 (WSA884X_ANA_BOOST_BASE + 0x04)
190 #define WSA884X_SPARE_RO_0 (WSA884X_ANA_BOOST_BASE + 0x05)
191 #define WSA884X_BOOST_SPARE_RO_1 (WSA884X_ANA_BOOST_BASE + 0x06)
192 #define WSA884X_IBIAS1 (WSA884X_ANA_BOOST_BASE + 0x07)
193 #define WSA884X_IBIAS2 (WSA884X_ANA_BOOST_BASE + 0x08)
194 #define WSA884X_IBIAS3 (WSA884X_ANA_BOOST_BASE + 0x09)
195 #define WSA884X_EN_CTRL (WSA884X_ANA_BOOST_BASE + 0x0a)
196 #define WSA884X_STB_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0b)
197 #define WSA884X_STB_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0c)
198 #define WSA884X_STB_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x0d)
199 #define WSA884X_BYP_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0e)
200 #define WSA884X_BYP_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0f)
201 #define WSA884X_ZX_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x10)
202 #define WSA884X_ZX_CTRL1_ZX_DET_EN_MASK 0x80
203 #define WSA884X_ZX_CTRL1_ZX_DET_EN_SHIFT 7
204 #define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_MASK 0x40
205 #define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_SHIFT 6
206 #define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_MASK 0x20
207 #define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_SHIFT 5
208 #define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK 0x18
209 #define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_SHIFT 3
210 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_MASK 0x04
211 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_SHIFT 2
212 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_MASK 0x02
213 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_SHIFT 1
214 #define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_MASK 0x01
215 #define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_SHIFT 0
216 #define WSA884X_ZX_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x11)
217 #define WSA884X_BLEEDER_CTRL (WSA884X_ANA_BOOST_BASE + 0x12)
218 #define WSA884X_BOOST_MISC (WSA884X_ANA_BOOST_BASE + 0x13)
219 #define WSA884X_PWRSTAGE_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x14)
220 #define WSA884X_PWRSTAGE_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x15)
221 #define WSA884X_PWRSTAGE_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x16)
222 #define WSA884X_PWRSTAGE_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x17)
223 #define WSA884X_MAXD_REG1 (WSA884X_ANA_BOOST_BASE + 0x18)
224 #define WSA884X_MAXD_REG2 (WSA884X_ANA_BOOST_BASE + 0x19)
225 #define WSA884X_ILIM_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1a)
226 #define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_MASK 0x80
227 #define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_SHIFT 0x07
228 #define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_MASK 0x40
229 #define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_SHIFT 0x06
230 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_MASK 0x38
231 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_SHIFT 0x03
232 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK 0x07
233 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_SHIFT 0x00
234 #define WSA884X_ILIM_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1b)
235 #define WSA884X_TEST_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1c)
236 #define WSA884X_TEST_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1d)
237 #define WSA884X_SPARE1 (WSA884X_ANA_BOOST_BASE + 0x1e)
238 #define WSA884X_BOOT_CAP_CHECK (WSA884X_ANA_BOOST_BASE + 0x1f)
239
240 #define WSA884X_ANA_PON_LDOL_BASE (WSA884X_BASE + 0x00b0)
241 #define WSA884X_PON_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x00)
242 #define WSA884X_PWRSAV_CTL (WSA884X_ANA_PON_LDOL_BASE + 0x01)
243 #define WSA884X_PON_LDOL_SPARE_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x02)
244 #define WSA884X_PON_LDOL_SPARE_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x03)
245 #define WSA884X_PON_LDOL_SPARE_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x04)
246 #define WSA884X_PON_LDOL_SPARE_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x05)
247 #define WSA884X_PON_CLT_1 (WSA884X_ANA_PON_LDOL_BASE + 0x06)
248 #define WSA884X_PON_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x07)
249 #define WSA884X_PON_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x08)
250 #define WSA884X_CKWD_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x09)
251 #define WSA884X_CKWD_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0a)
252 #define WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK 0x20
253 #define WSA884X_CKWD_CTL_1_VPP_SW_CTL_SHIFT 5
254 #define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f
255 #define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0
256 #define WSA884X_CKWD_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x0b)
257 #define WSA884X_CKSK_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0c)
258 #define WSA884X_PADSW_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0d)
259 #define WSA884X_TEST_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0e)
260 #define WSA884X_TEST_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0f)
261 #define WSA884X_STATUS_0 (WSA884X_ANA_PON_LDOL_BASE + 0x10)
262 #define WSA884X_STATUS_1 (WSA884X_ANA_PON_LDOL_BASE + 0x11)
263 #define WSA884X_PON_LDOL_SPARE_TUNE_0 (WSA884X_ANA_PON_LDOL_BASE + 0x12)
264 #define WSA884X_PON_LDOL_SPARE_TUNE_1 (WSA884X_ANA_PON_LDOL_BASE + 0x13)
265 #define WSA884X_PON_LDOL_SPARE_TUNE_2 (WSA884X_ANA_PON_LDOL_BASE + 0x14)
266 #define WSA884X_PON_LDOL_SPARE_TUNE_3 (WSA884X_ANA_PON_LDOL_BASE + 0x15)
267 #define WSA884X_PON_LDOL_SPARE_TUNE_4 (WSA884X_ANA_PON_LDOL_BASE + 0x16)
268
269 #define WSA884X_DIG_CTRL0_BASE (WSA884X_BASE + 0x0400)
270 #define WSA884X_DIG_CTRL0_PAGE (WSA884X_DIG_CTRL0_BASE + 0x00)
271 #define WSA884X_CHIP_ID0 (WSA884X_DIG_CTRL0_BASE + 0x01)
272 #define WSA884X_CHIP_ID1 (WSA884X_DIG_CTRL0_BASE + 0x02)
273 #define WSA884X_CHIP_ID2 (WSA884X_DIG_CTRL0_BASE + 0x03)
274 #define WSA884X_CHIP_ID3 (WSA884X_DIG_CTRL0_BASE + 0x04)
275 #define WSA884X_BUS_ID (WSA884X_DIG_CTRL0_BASE + 0x05)
276 #define WSA884X_CDC_RST_CTL (WSA884X_DIG_CTRL0_BASE + 0x10)
277 #define WSA884X_SWR_RESET_EN (WSA884X_DIG_CTRL0_BASE + 0x14)
278 #define WSA884X_TOP_CLK_CFG (WSA884X_DIG_CTRL0_BASE + 0x18)
279 #define WSA884X_SWR_CLK_RATE (WSA884X_DIG_CTRL0_BASE + 0x19)
280 #define WSA884X_CDC_PATH_MODE (WSA884X_DIG_CTRL0_BASE + 0x1a)
281 #define WSA884X_CDC_PATH_MODE_RXD_MODE_MASK 0x02
282 #define WSA884X_CDC_PATH_MODE_RXD_MODE_SHIFT 0
283 #define WSA884X_CDC_PATH_MODE_TXD_MODE_MASK 0x01
284 #define WSA884X_CDC_PATH_MODE_TXD_MODE_SHIFT 0
285 #define WSA884X_CDC_CLK_CTL (WSA884X_DIG_CTRL0_BASE + 0x1c)
286 #define WSA884X_PA_FSM_EN (WSA884X_DIG_CTRL0_BASE + 0x30)
287 #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01
288 #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0
289 #define WSA884X_PA_FSM_CTL0 (WSA884X_DIG_CTRL0_BASE + 0x31)
290 #define WSA884X_PA_FSM_CTL1 (WSA884X_DIG_CTRL0_BASE + 0x32)
291 #define WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK 0x38
292 #define WSA884X_PA_FSM_TIMER0 (WSA884X_DIG_CTRL0_BASE + 0x33)
293 #define WSA884X_PA_FSM_TIMER1 (WSA884X_DIG_CTRL0_BASE + 0x34)
294 #define WSA884X_PA_FSM_STA0 (WSA884X_DIG_CTRL0_BASE + 0x35)
295 #define WSA884X_PA_FSM_STA1 (WSA884X_DIG_CTRL0_BASE + 0x36)
296 #define WSA884X_PA_FSM_ERR_CTL (WSA884X_DIG_CTRL0_BASE + 0x37)
297 #define WSA884X_PA_FSM_ERR_COND0 (WSA884X_DIG_CTRL0_BASE + 0x38)
298 #define WSA884X_PA_FSM_ERR_COND1 (WSA884X_DIG_CTRL0_BASE + 0x39)
299 #define WSA884X_PA_FSM_MSK0 (WSA884X_DIG_CTRL0_BASE + 0x3a)
300 #define WSA884X_PA_FSM_MSK1 (WSA884X_DIG_CTRL0_BASE + 0x3b)
301 #define WSA884X_PA_FSM_BYP_CTL (WSA884X_DIG_CTRL0_BASE + 0x3c)
302 #define WSA884X_PA_FSM_BYP0 (WSA884X_DIG_CTRL0_BASE + 0x3d)
303 #define WSA884X_PA_FSM_BYP1 (WSA884X_DIG_CTRL0_BASE + 0x3e)
304 #define WSA884X_TADC_VALUE_CTL (WSA884X_DIG_CTRL0_BASE + 0x50)
305 #define WSA884X_TEMP_DETECT_CTL (WSA884X_DIG_CTRL0_BASE + 0x51)
306 #define WSA884X_TEMP_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x52)
307 #define WSA884X_TEMP_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x53)
308 #define WSA884X_TEMP_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x54)
309 #define WSA884X_TEMP_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x55)
310 #define WSA884X_TEMP_CONFIG0 (WSA884X_DIG_CTRL0_BASE + 0x56)
311 #define WSA884X_TEMP_CONFIG1 (WSA884X_DIG_CTRL0_BASE + 0x57)
312 #define WSA884X_VBAT_THRM_FLT_CTL (WSA884X_DIG_CTRL0_BASE + 0x58)
313 #define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK 0xe0
314 #define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_SHIFT 5
315 #define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_SHIFT 4
316 #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e
317 #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 1
318 #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0
319 #define WSA884X_VBAT_CAL_CTL (WSA884X_DIG_CTRL0_BASE + 0x59)
320 #define WSA884X_VBAT_CAL_CTL_RESERVE_MASK 0x0e
321 #define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK 0x01
322 #define WSA884X_VBAT_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x5a)
323 #define WSA884X_VBAT_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x5b)
324 #define WSA884X_VBAT_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x5c)
325 #define WSA884X_VBAT_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x5d)
326 #define WSA884X_VBAT_CAL_MSB (WSA884X_DIG_CTRL0_BASE + 0x5e)
327 #define WSA884X_VBAT_CAL_LSB (WSA884X_DIG_CTRL0_BASE + 0x5f)
328 #define WSA884X_UVLO_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x60)
329 #define WSA884X_BOP_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x61)
330 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK 0x1e
331 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 1
332 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK 0x1
333 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0
334 #define WSA884X_VBAT_ZONE_DETC_CTL (WSA884X_DIG_CTRL0_BASE + 0x64)
335 #define WSA884X_CPS_CTL (WSA884X_DIG_CTRL0_BASE + 0x68)
336 #define WSA884X_CDC_RX_CTL (WSA884X_DIG_CTRL0_BASE + 0x70)
337 #define WSA884X_CDC_SPK_DSM_A1_0 (WSA884X_DIG_CTRL0_BASE + 0x71)
338 #define WSA884X_CDC_SPK_DSM_A1_1 (WSA884X_DIG_CTRL0_BASE + 0x72)
339 #define WSA884X_CDC_SPK_DSM_A2_0 (WSA884X_DIG_CTRL0_BASE + 0x73)
340 #define WSA884X_CDC_SPK_DSM_A2_1 (WSA884X_DIG_CTRL0_BASE + 0x74)
341 #define WSA884X_CDC_SPK_DSM_A3_0 (WSA884X_DIG_CTRL0_BASE + 0x75)
342 #define WSA884X_CDC_SPK_DSM_A3_1 (WSA884X_DIG_CTRL0_BASE + 0x76)
343 #define WSA884X_CDC_SPK_DSM_A4_0 (WSA884X_DIG_CTRL0_BASE + 0x77)
344 #define WSA884X_CDC_SPK_DSM_A4_1 (WSA884X_DIG_CTRL0_BASE + 0x78)
345 #define WSA884X_CDC_SPK_DSM_A5_0 (WSA884X_DIG_CTRL0_BASE + 0x79)
346 #define WSA884X_CDC_SPK_DSM_A5_1 (WSA884X_DIG_CTRL0_BASE + 0x7a)
347 #define WSA884X_CDC_SPK_DSM_A6_0 (WSA884X_DIG_CTRL0_BASE + 0x7b)
348 #define WSA884X_CDC_SPK_DSM_A7_0 (WSA884X_DIG_CTRL0_BASE + 0x7c)
349 #define WSA884X_CDC_SPK_DSM_C_0 (WSA884X_DIG_CTRL0_BASE + 0x7d)
350 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0
351 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 4
352 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f
353 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0
354 #define WSA884X_CDC_SPK_DSM_C_1 (WSA884X_DIG_CTRL0_BASE + 0x7e)
355 #define WSA884X_CDC_SPK_DSM_C_2 (WSA884X_DIG_CTRL0_BASE + 0x7f)
356 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0
357 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 4
358 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f
359 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0
360 #define WSA884X_CDC_SPK_DSM_C_3 (WSA884X_DIG_CTRL0_BASE + 0x80)
361 #define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f
362 #define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0
363 #define WSA884X_CDC_SPK_DSM_R1 (WSA884X_DIG_CTRL0_BASE + 0x81)
364 #define WSA884X_CDC_SPK_DSM_R2 (WSA884X_DIG_CTRL0_BASE + 0x82)
365 #define WSA884X_CDC_SPK_DSM_R3 (WSA884X_DIG_CTRL0_BASE + 0x83)
366 #define WSA884X_CDC_SPK_DSM_R4 (WSA884X_DIG_CTRL0_BASE + 0x84)
367 #define WSA884X_CDC_SPK_DSM_R5 (WSA884X_DIG_CTRL0_BASE + 0x85)
368 #define WSA884X_CDC_SPK_DSM_R6 (WSA884X_DIG_CTRL0_BASE + 0x86)
369 #define WSA884X_CDC_SPK_DSM_R7 (WSA884X_DIG_CTRL0_BASE + 0x87)
370 #define WSA884X_CDC_SPK_GAIN_PDM_0 (WSA884X_DIG_CTRL0_BASE + 0x88)
371 #define WSA884X_CDC_SPK_GAIN_PDM_1 (WSA884X_DIG_CTRL0_BASE + 0x89)
372 #define WSA884X_CDC_SPK_GAIN_PDM_2 (WSA884X_DIG_CTRL0_BASE + 0x8a)
373 #define WSA884X_PDM_WD_CTL (WSA884X_DIG_CTRL0_BASE + 0x8b)
374 #define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK 0x04
375 #define WSA884X_PDM_WD_CTL_HOLD_OFF_SHIFT 2
376 #define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK 0x02
377 #define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_SHIFT 1
378 #define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01
379 #define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0
380 #define WSA884X_DEM_BYPASS_DATA0 (WSA884X_DIG_CTRL0_BASE + 0x90)
381 #define WSA884X_DEM_BYPASS_DATA1 (WSA884X_DIG_CTRL0_BASE + 0x91)
382 #define WSA884X_DEM_BYPASS_DATA2 (WSA884X_DIG_CTRL0_BASE + 0x92)
383 #define WSA884X_DEM_BYPASS_DATA3 (WSA884X_DIG_CTRL0_BASE + 0x93)
384 #define WSA884X_DRE_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xb0)
385 #define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0
386 #define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 4
387 #define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07
388 #define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0
389 #define WSA884X_DRE_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xb1)
390 #define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e
391 #define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 1
392 #define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01
393 #define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0
394 #define WSA884X_DRE_IDLE_DET_CTL (WSA884X_DIG_CTRL0_BASE + 0xb2)
395 #define WSA884X_GAIN_RAMPING_CTL (WSA884X_DIG_CTRL0_BASE + 0xb8)
396 #define WSA884X_GAIN_RAMPING_MIN (WSA884X_DIG_CTRL0_BASE + 0xb9)
397 #define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK 0x1f
398 #define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_SHIFT 0
399 #define WSA884X_TAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc0)
400 #define WSA884X_TAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc1)
401 #define WSA884X_TAGC_FORCE_VAL (WSA884X_DIG_CTRL0_BASE + 0xc2)
402 #define WSA884X_VAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc8)
403 #define WSA884X_VAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc9)
404 #define WSA884X_VAGC_ATTN_LVL_1 (WSA884X_DIG_CTRL0_BASE + 0xca)
405 #define WSA884X_VAGC_ATTN_LVL_2 (WSA884X_DIG_CTRL0_BASE + 0xcb)
406 #define WSA884X_VAGC_ATTN_LVL_3 (WSA884X_DIG_CTRL0_BASE + 0xcc)
407 #define WSA884X_CLSH_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xd0)
408 #define WSA884X_CLSH_CTL_0_CSR_GAIN_EN_SHIFT 7
409 #define WSA884X_CLSH_CTL_0_DLY_CODE_MASK 0x70
410 #define WSA884X_CLSH_CTL_0_DLY_CODE_SHIFT 4
411 #define WSA884X_CLSH_CTL_0_DLY_RST_SHIFT 3
412 #define WSA884X_CLSH_CTL_0_DLY_EN_SHIFT 2
413 #define WSA884X_CLSH_CTL_0_INPUT_EN_SHIFT 1
414 #define WSA884X_CLSH_CTL_0_CLSH_EN_SHIFT 0
415 #define WSA884X_CLSH_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xd1)
416 #define WSA884X_CLSH_V_HD_PA (WSA884X_DIG_CTRL0_BASE + 0xd2)
417 #define WSA884X_CLSH_V_PA_MIN (WSA884X_DIG_CTRL0_BASE + 0xd3)
418 #define WSA884X_CLSH_OVRD_VAL (WSA884X_DIG_CTRL0_BASE + 0xd4)
419 #define WSA884X_CLSH_HARD_MAX (WSA884X_DIG_CTRL0_BASE + 0xd5)
420 #define WSA884X_CLSH_SOFT_MAX (WSA884X_DIG_CTRL0_BASE + 0xd6)
421 #define WSA884X_CLSH_SIG_DP (WSA884X_DIG_CTRL0_BASE + 0xd7)
422 #define WSA884X_PBR_DELAY_CTL (WSA884X_DIG_CTRL0_BASE + 0xd8)
423 #define WSA884X_CLSH_SRL_MAX_PBR (WSA884X_DIG_CTRL0_BASE + 0xe0)
424 #define WSA884X_PBR_MAX_VOLTAGE 20
425 #define WSA884X_PBR_MAX_CODE 255
426 #define WSA884X_VTH_TO_REG(vth) \
427 ((vth) != 0 ? (((vth) - 150) * WSA884X_PBR_MAX_CODE / (WSA884X_PBR_MAX_VOLTAGE * 100) + 1) : 0)
428 #define WSA884X_CLSH_VTH1 (WSA884X_DIG_CTRL0_BASE + 0xe1)
429 #define WSA884X_CLSH_VTH2 (WSA884X_DIG_CTRL0_BASE + 0xe2)
430 #define WSA884X_CLSH_VTH3 (WSA884X_DIG_CTRL0_BASE + 0xe3)
431 #define WSA884X_CLSH_VTH4 (WSA884X_DIG_CTRL0_BASE + 0xe4)
432 #define WSA884X_CLSH_VTH5 (WSA884X_DIG_CTRL0_BASE + 0xe5)
433 #define WSA884X_CLSH_VTH6 (WSA884X_DIG_CTRL0_BASE + 0xe6)
434 #define WSA884X_CLSH_VTH7 (WSA884X_DIG_CTRL0_BASE + 0xe7)
435 #define WSA884X_CLSH_VTH8 (WSA884X_DIG_CTRL0_BASE + 0xe8)
436 #define WSA884X_CLSH_VTH9 (WSA884X_DIG_CTRL0_BASE + 0xe9)
437 #define WSA884X_CLSH_VTH10 (WSA884X_DIG_CTRL0_BASE + 0xea)
438 #define WSA884X_CLSH_VTH11 (WSA884X_DIG_CTRL0_BASE + 0xeb)
439 #define WSA884X_CLSH_VTH12 (WSA884X_DIG_CTRL0_BASE + 0xec)
440 #define WSA884X_CLSH_VTH13 (WSA884X_DIG_CTRL0_BASE + 0xed)
441 #define WSA884X_CLSH_VTH14 (WSA884X_DIG_CTRL0_BASE + 0xee)
442 #define WSA884X_CLSH_VTH15 (WSA884X_DIG_CTRL0_BASE + 0xef)
443
444 #define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE + 0x0500)
445 #define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE + 0x00)
446 #define WSA884X_VPHX_SYS_EN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x01)
447 #define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE + 0x04)
448 #define WSA884X_ANA_WO_CTL_0_MODE_SHIFT 0
449 #define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK 0xc0
450 #define WSA884X_ANA_WO_CTL_0_PA_AUX_DISABLE 0x0
451 #define WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB 0xa
452 #define WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB 0x7
453 #define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK 0x3c
454 #define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK 0x02
455 #define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER 0x1
456 #define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK 0x01
457 #define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE + 0x05)
458 #define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE + 0x10)
459 #define WSA884X_PIN_CTL_OE (WSA884X_DIG_CTRL1_BASE + 0x11)
460 #define WSA884X_PIN_WDATA_IOPAD (WSA884X_DIG_CTRL1_BASE + 0x12)
461 #define WSA884X_PIN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x13)
462 #define WSA884X_I2C_SLAVE_CTL (WSA884X_DIG_CTRL1_BASE + 0x14)
463 #define WSA884X_SPMI_PAD_CTL0 (WSA884X_DIG_CTRL1_BASE + 0x15)
464 #define WSA884X_SPMI_PAD_CTL1 (WSA884X_DIG_CTRL1_BASE + 0x16)
465 #define WSA884X_SPMI_PAD_CTL2 (WSA884X_DIG_CTRL1_BASE + 0x17)
466 #define WSA884X_MEM_CTL (WSA884X_DIG_CTRL1_BASE + 0x18)
467 #define WSA884X_SWR_HM_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x19)
468 #define WSA884X_SWR_HM_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x1a)
469 #define WSA884X_OTP_CTRL0 (WSA884X_DIG_CTRL1_BASE + 0x30)
470 #define WSA884X_OTP_CTRL1 (WSA884X_DIG_CTRL1_BASE + 0x31)
471 #define WSA884X_OTP_CTRL2 (WSA884X_DIG_CTRL1_BASE + 0x32)
472 #define WSA884X_OTP_STAT (WSA884X_DIG_CTRL1_BASE + 0x33)
473 #define WSA884X_OTP_PRG_TCSP0 (WSA884X_DIG_CTRL1_BASE + 0x34)
474 #define WSA884X_OTP_PRG_TCSP1 (WSA884X_DIG_CTRL1_BASE + 0x35)
475 #define WSA884X_OTP_PRG_TPPS (WSA884X_DIG_CTRL1_BASE + 0x36)
476 #define WSA884X_OTP_PRG_TVPS (WSA884X_DIG_CTRL1_BASE + 0x37)
477 #define WSA884X_OTP_PRG_TVPH (WSA884X_DIG_CTRL1_BASE + 0x38)
478 #define WSA884X_OTP_PRG_TPPR0 (WSA884X_DIG_CTRL1_BASE + 0x39)
479 #define WSA884X_OTP_PRG_TPPR1 (WSA884X_DIG_CTRL1_BASE + 0x3a)
480 #define WSA884X_OTP_PRG_TPPH (WSA884X_DIG_CTRL1_BASE + 0x3b)
481 #define WSA884X_OTP_PRG_END (WSA884X_DIG_CTRL1_BASE + 0x3c)
482 #define WSA884X_WAVG_PLAY (WSA884X_DIG_CTRL1_BASE + 0x40)
483 #define WSA884X_WAVG_CTL (WSA884X_DIG_CTRL1_BASE + 0x41)
484 #define WSA884X_WAVG_LRA_PER_0 (WSA884X_DIG_CTRL1_BASE + 0x43)
485 #define WSA884X_WAVG_LRA_PER_1 (WSA884X_DIG_CTRL1_BASE + 0x44)
486 #define WSA884X_WAVG_DELTA_THETA_0 (WSA884X_DIG_CTRL1_BASE + 0x45)
487 #define WSA884X_WAVG_DELTA_THETA_1 (WSA884X_DIG_CTRL1_BASE + 0x46)
488 #define WSA884X_WAVG_DIRECT_AMP_0 (WSA884X_DIG_CTRL1_BASE + 0x47)
489 #define WSA884X_WAVG_DIRECT_AMP_1 (WSA884X_DIG_CTRL1_BASE + 0x48)
490 #define WSA884X_WAVG_PTRN_AMP0_0 (WSA884X_DIG_CTRL1_BASE + 0x49)
491 #define WSA884X_WAVG_PTRN_AMP0_1 (WSA884X_DIG_CTRL1_BASE + 0x4a)
492 #define WSA884X_WAVG_PTRN_AMP1_0 (WSA884X_DIG_CTRL1_BASE + 0x4b)
493 #define WSA884X_WAVG_PTRN_AMP1_1 (WSA884X_DIG_CTRL1_BASE + 0x4c)
494 #define WSA884X_WAVG_PTRN_AMP2_0 (WSA884X_DIG_CTRL1_BASE + 0x4d)
495 #define WSA884X_WAVG_PTRN_AMP2_1 (WSA884X_DIG_CTRL1_BASE + 0x4e)
496 #define WSA884X_WAVG_PTRN_AMP3_0 (WSA884X_DIG_CTRL1_BASE + 0x4f)
497 #define WSA884X_WAVG_PTRN_AMP3_1 (WSA884X_DIG_CTRL1_BASE + 0x50)
498 #define WSA884X_WAVG_PTRN_AMP4_0 (WSA884X_DIG_CTRL1_BASE + 0x51)
499 #define WSA884X_WAVG_PTRN_AMP4_1 (WSA884X_DIG_CTRL1_BASE + 0x52)
500 #define WSA884X_WAVG_PTRN_AMP5_0 (WSA884X_DIG_CTRL1_BASE + 0x53)
501 #define WSA884X_WAVG_PTRN_AMP5_1 (WSA884X_DIG_CTRL1_BASE + 0x54)
502 #define WSA884X_WAVG_PTRN_AMP6_0 (WSA884X_DIG_CTRL1_BASE + 0x55)
503 #define WSA884X_WAVG_PTRN_AMP6_1 (WSA884X_DIG_CTRL1_BASE + 0x56)
504 #define WSA884X_WAVG_PTRN_AMP7_0 (WSA884X_DIG_CTRL1_BASE + 0x57)
505 #define WSA884X_WAVG_PTRN_AMP7_1 (WSA884X_DIG_CTRL1_BASE + 0x58)
506 #define WSA884X_WAVG_PER_0_1 (WSA884X_DIG_CTRL1_BASE + 0x59)
507 #define WSA884X_WAVG_PER_2_3 (WSA884X_DIG_CTRL1_BASE + 0x5a)
508 #define WSA884X_WAVG_PER_4_5 (WSA884X_DIG_CTRL1_BASE + 0x5b)
509 #define WSA884X_WAVG_PER_6_7 (WSA884X_DIG_CTRL1_BASE + 0x5c)
510 #define WSA884X_WAVG_STA (WSA884X_DIG_CTRL1_BASE + 0x5d)
511 #define WSA884X_INTR_MODE (WSA884X_DIG_CTRL1_BASE + 0x80)
512 #define WSA884X_INTR_MASK0 (WSA884X_DIG_CTRL1_BASE + 0x81)
513 #define WSA884X_INTR_MASK1 (WSA884X_DIG_CTRL1_BASE + 0x82)
514 #define WSA884X_INTR_STATUS0 (WSA884X_DIG_CTRL1_BASE + 0x83)
515 #define WSA884X_INTR_STATUS1 (WSA884X_DIG_CTRL1_BASE + 0x84)
516 #define WSA884X_INTR_CLEAR0 (WSA884X_DIG_CTRL1_BASE + 0x85)
517 #define WSA884X_INTR_CLEAR1 (WSA884X_DIG_CTRL1_BASE + 0x86)
518 #define WSA884X_INTR_LEVEL0 (WSA884X_DIG_CTRL1_BASE + 0x87)
519 #define WSA884X_INTR_LEVEL1 (WSA884X_DIG_CTRL1_BASE + 0x88)
520 #define WSA884X_INTR_SET0 (WSA884X_DIG_CTRL1_BASE + 0x89)
521 #define WSA884X_INTR_SET1 (WSA884X_DIG_CTRL1_BASE + 0x8a)
522 #define WSA884X_INTR_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x8b)
523 #define WSA884X_INTR_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x8c)
524 #define WSA884X_PDM_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc0)
525 #define WSA884X_ATE_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc1)
526 #define WSA884X_PA_FSM_DBG (WSA884X_DIG_CTRL1_BASE + 0xc2)
527 #define WSA884X_DIG_DEBUG_MODE (WSA884X_DIG_CTRL1_BASE + 0xc3)
528 #define WSA884X_DIG_DEBUG_SEL (WSA884X_DIG_CTRL1_BASE + 0xc4)
529 #define WSA884X_DIG_DEBUG_EN (WSA884X_DIG_CTRL1_BASE + 0xc5)
530 #define WSA884X_TADC_DETECT_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xc9)
531 #define WSA884X_TADC_DEBUG_MSB (WSA884X_DIG_CTRL1_BASE + 0xca)
532 #define WSA884X_TADC_DEBUG_LSB (WSA884X_DIG_CTRL1_BASE + 0xcb)
533 #define WSA884X_SAMPLE_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcc)
534 #define WSA884X_SWR_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcd)
535 #define WSA884X_TEST_MODE_CTL (WSA884X_DIG_CTRL1_BASE + 0xce)
536 #define WSA884X_IOPAD_CTL (WSA884X_DIG_CTRL1_BASE + 0xcf)
537 #define WSA884X_ANA_CSR_DBG_ADD (WSA884X_DIG_CTRL1_BASE + 0xd0)
538 #define WSA884X_ANA_CSR_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd1)
539 #define WSA884X_CLK_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd2)
540 #define WSA884X_SPARE_R (WSA884X_DIG_CTRL1_BASE + 0xf0)
541 #define WSA884X_SPARE_0 (WSA884X_DIG_CTRL1_BASE + 0xf1)
542 #define WSA884X_SPARE_1 (WSA884X_DIG_CTRL1_BASE + 0xf2)
543 #define WSA884X_SPARE_2 (WSA884X_DIG_CTRL1_BASE + 0xf3)
544 #define WSA884X_SCODE (WSA884X_DIG_CTRL1_BASE + 0xff)
545
546 #define WSA884X_DIG_TRIM_BASE (WSA884X_BASE + 0x0800)
547 #define WSA884X_DIG_TRIM_PAGE (WSA884X_DIG_TRIM_BASE + 0x00)
548 #define WSA884X_OTP_REG_0 (WSA884X_DIG_TRIM_BASE + 0x80)
549 #define WSA884X_OTP_ID_WSA8840 0x0
550 #define WSA884X_OTP_ID_WSA8845 0x5
551 #define WSA884X_OTP_ID_WSA8845H 0xc
552 #define WSA884X_OTP_REG_0_ID_MASK 0x0f
553 #define WSA884X_OTP_REG_1 (WSA884X_DIG_TRIM_BASE + 0x81)
554 #define WSA884X_OTP_REG_2 (WSA884X_DIG_TRIM_BASE + 0x82)
555 #define WSA884X_OTP_REG_3 (WSA884X_DIG_TRIM_BASE + 0x83)
556 #define WSA884X_OTP_REG_4 (WSA884X_DIG_TRIM_BASE + 0x84)
557 #define WSA884X_OTP_REG_5 (WSA884X_DIG_TRIM_BASE + 0x85)
558 #define WSA884X_OTP_REG_6 (WSA884X_DIG_TRIM_BASE + 0x86)
559 #define WSA884X_OTP_REG_7 (WSA884X_DIG_TRIM_BASE + 0x87)
560 #define WSA884X_OTP_REG_8 (WSA884X_DIG_TRIM_BASE + 0x88)
561 #define WSA884X_OTP_REG_9 (WSA884X_DIG_TRIM_BASE + 0x89)
562 #define WSA884X_OTP_REG_10 (WSA884X_DIG_TRIM_BASE + 0x8a)
563 #define WSA884X_OTP_REG_11 (WSA884X_DIG_TRIM_BASE + 0x8b)
564 #define WSA884X_OTP_REG_12 (WSA884X_DIG_TRIM_BASE + 0x8c)
565 #define WSA884X_OTP_REG_13 (WSA884X_DIG_TRIM_BASE + 0x8d)
566 #define WSA884X_OTP_REG_14 (WSA884X_DIG_TRIM_BASE + 0x8e)
567 #define WSA884X_OTP_REG_15 (WSA884X_DIG_TRIM_BASE + 0x8f)
568 #define WSA884X_OTP_REG_16 (WSA884X_DIG_TRIM_BASE + 0x90)
569 #define WSA884X_OTP_REG_17 (WSA884X_DIG_TRIM_BASE + 0x91)
570 #define WSA884X_OTP_REG_18 (WSA884X_DIG_TRIM_BASE + 0x92)
571 #define WSA884X_OTP_REG_19 (WSA884X_DIG_TRIM_BASE + 0x93)
572 #define WSA884X_OTP_REG_20 (WSA884X_DIG_TRIM_BASE + 0x94)
573 #define WSA884X_OTP_REG_21 (WSA884X_DIG_TRIM_BASE + 0x95)
574 #define WSA884X_OTP_REG_22 (WSA884X_DIG_TRIM_BASE + 0x96)
575 #define WSA884X_OTP_REG_23 (WSA884X_DIG_TRIM_BASE + 0x97)
576 #define WSA884X_OTP_REG_24 (WSA884X_DIG_TRIM_BASE + 0x98)
577 #define WSA884X_OTP_REG_25 (WSA884X_DIG_TRIM_BASE + 0x99)
578 #define WSA884X_OTP_REG_26 (WSA884X_DIG_TRIM_BASE + 0x9a)
579 #define WSA884X_OTP_REG_27 (WSA884X_DIG_TRIM_BASE + 0x9b)
580 #define WSA884X_OTP_REG_28 (WSA884X_DIG_TRIM_BASE + 0x9c)
581 #define WSA884X_OTP_REG_29 (WSA884X_DIG_TRIM_BASE + 0x9d)
582 #define WSA884X_OTP_REG_30 (WSA884X_DIG_TRIM_BASE + 0x9e)
583 #define WSA884X_OTP_REG_31 (WSA884X_DIG_TRIM_BASE + 0x9f)
584 #define WSA884X_OTP_REG_32 (WSA884X_DIG_TRIM_BASE + 0xa0)
585 #define WSA884X_OTP_REG_33 (WSA884X_DIG_TRIM_BASE + 0xa1)
586 #define WSA884X_OTP_REG_34 (WSA884X_DIG_TRIM_BASE + 0xa2)
587 #define WSA884X_OTP_REG_35 (WSA884X_DIG_TRIM_BASE + 0xa3)
588 #define WSA884X_OTP_REG_36 (WSA884X_DIG_TRIM_BASE + 0xa4)
589 #define WSA884X_OTP_REG_37 (WSA884X_DIG_TRIM_BASE + 0xa5)
590 #define WSA884X_OTP_REG_38 (WSA884X_DIG_TRIM_BASE + 0xa6)
591 #define WSA884X_OTP_REG_38_RESERVER_MASK 0xf0
592 #define WSA884X_OTP_REG_38_RESERVER_SHIFT 4
593 #define WSA884X_OTP_REG_38_BST_CFG_SEL_MASK 0x08
594 #define WSA884X_OTP_REG_38_BST_CFG_SEL_SHIFT 3
595 #define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_MASK 0x07
596 #define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_SHIFT 0
597 #define WSA884X_OTP_REG_39 (WSA884X_DIG_TRIM_BASE + 0xa7)
598 #define WSA884X_OTP_REG_40 (WSA884X_DIG_TRIM_BASE + 0xa8)
599 #define WSA884X_OTP_REG_40_SPARE_TYPE2_MASK 0xc0
600 #define WSA884X_OTP_REG_40_SPARE_TYPE2_SHIFT 6
601 #define WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK 0x3c
602 #define WSA884X_OTP_REG_40_ISENSE_RESCAL_SHIFT 2
603 #define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_MASK 0x2
604 #define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_SHIFT 1
605 #define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_MASK 0x1
606 #define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_SHIFT 0
607 #define WSA884X_OTP_REG_41 (WSA884X_DIG_TRIM_BASE + 0xa9)
608 #define WSA884X_OTP_REG_63 (WSA884X_DIG_TRIM_BASE + 0xbf)
609
610 #define WSA884X_DIG_EMEM_BASE (WSA884X_BASE + 0x08C0)
611 #define WSA884X_EMEM_0 (WSA884X_DIG_EMEM_BASE + 0x00)
612 #define WSA884X_EMEM_1 (WSA884X_DIG_EMEM_BASE + 0x01)
613 #define WSA884X_EMEM_2 (WSA884X_DIG_EMEM_BASE + 0x02)
614 #define WSA884X_EMEM_3 (WSA884X_DIG_EMEM_BASE + 0x03)
615 #define WSA884X_EMEM_4 (WSA884X_DIG_EMEM_BASE + 0x04)
616 #define WSA884X_EMEM_5 (WSA884X_DIG_EMEM_BASE + 0x05)
617 #define WSA884X_EMEM_6 (WSA884X_DIG_EMEM_BASE + 0x06)
618 #define WSA884X_EMEM_7 (WSA884X_DIG_EMEM_BASE + 0x07)
619 #define WSA884X_EMEM_8 (WSA884X_DIG_EMEM_BASE + 0x08)
620 #define WSA884X_EMEM_9 (WSA884X_DIG_EMEM_BASE + 0x09)
621 #define WSA884X_EMEM_10 (WSA884X_DIG_EMEM_BASE + 0x0a)
622 #define WSA884X_EMEM_11 (WSA884X_DIG_EMEM_BASE + 0x0b)
623 #define WSA884X_EMEM_12 (WSA884X_DIG_EMEM_BASE + 0x0c)
624 #define WSA884X_EMEM_13 (WSA884X_DIG_EMEM_BASE + 0x0d)
625 #define WSA884X_EMEM_14 (WSA884X_DIG_EMEM_BASE + 0x0e)
626 #define WSA884X_EMEM_15 (WSA884X_DIG_EMEM_BASE + 0x0f)
627 #define WSA884X_EMEM_16 (WSA884X_DIG_EMEM_BASE + 0x10)
628 #define WSA884X_EMEM_17 (WSA884X_DIG_EMEM_BASE + 0x11)
629 #define WSA884X_EMEM_18 (WSA884X_DIG_EMEM_BASE + 0x12)
630 #define WSA884X_EMEM_19 (WSA884X_DIG_EMEM_BASE + 0x13)
631 #define WSA884X_EMEM_20 (WSA884X_DIG_EMEM_BASE + 0x14)
632 #define WSA884X_EMEM_21 (WSA884X_DIG_EMEM_BASE + 0x15)
633 #define WSA884X_EMEM_22 (WSA884X_DIG_EMEM_BASE + 0x16)
634 #define WSA884X_EMEM_23 (WSA884X_DIG_EMEM_BASE + 0x17)
635 #define WSA884X_EMEM_24 (WSA884X_DIG_EMEM_BASE + 0x18)
636 #define WSA884X_EMEM_25 (WSA884X_DIG_EMEM_BASE + 0x19)
637 #define WSA884X_EMEM_26 (WSA884X_DIG_EMEM_BASE + 0x1a)
638 #define WSA884X_EMEM_27 (WSA884X_DIG_EMEM_BASE + 0x1b)
639 #define WSA884X_EMEM_28 (WSA884X_DIG_EMEM_BASE + 0x1c)
640 #define WSA884X_EMEM_29 (WSA884X_DIG_EMEM_BASE + 0x1d)
641 #define WSA884X_EMEM_30 (WSA884X_DIG_EMEM_BASE + 0x1e)
642 #define WSA884X_EMEM_31 (WSA884X_DIG_EMEM_BASE + 0x1f)
643 #define WSA884X_EMEM_32 (WSA884X_DIG_EMEM_BASE + 0x20)
644 #define WSA884X_EMEM_33 (WSA884X_DIG_EMEM_BASE + 0x21)
645 #define WSA884X_EMEM_34 (WSA884X_DIG_EMEM_BASE + 0x22)
646 #define WSA884X_EMEM_35 (WSA884X_DIG_EMEM_BASE + 0x23)
647 #define WSA884X_EMEM_36 (WSA884X_DIG_EMEM_BASE + 0x24)
648 #define WSA884X_EMEM_37 (WSA884X_DIG_EMEM_BASE + 0x25)
649 #define WSA884X_EMEM_38 (WSA884X_DIG_EMEM_BASE + 0x26)
650 #define WSA884X_EMEM_39 (WSA884X_DIG_EMEM_BASE + 0x27)
651 #define WSA884X_EMEM_40 (WSA884X_DIG_EMEM_BASE + 0x28)
652 #define WSA884X_EMEM_41 (WSA884X_DIG_EMEM_BASE + 0x29)
653 #define WSA884X_EMEM_42 (WSA884X_DIG_EMEM_BASE + 0x2a)
654 #define WSA884X_EMEM_43 (WSA884X_DIG_EMEM_BASE + 0x2b)
655 #define WSA884X_EMEM_44 (WSA884X_DIG_EMEM_BASE + 0x2c)
656 #define WSA884X_EMEM_45 (WSA884X_DIG_EMEM_BASE + 0x2d)
657 #define WSA884X_EMEM_46 (WSA884X_DIG_EMEM_BASE + 0x2e)
658 #define WSA884X_EMEM_47 (WSA884X_DIG_EMEM_BASE + 0x2f)
659 #define WSA884X_EMEM_48 (WSA884X_DIG_EMEM_BASE + 0x30)
660 #define WSA884X_EMEM_49 (WSA884X_DIG_EMEM_BASE + 0x31)
661 #define WSA884X_EMEM_50 (WSA884X_DIG_EMEM_BASE + 0x32)
662 #define WSA884X_EMEM_51 (WSA884X_DIG_EMEM_BASE + 0x33)
663 #define WSA884X_EMEM_52 (WSA884X_DIG_EMEM_BASE + 0x34)
664 #define WSA884X_EMEM_53 (WSA884X_DIG_EMEM_BASE + 0x35)
665 #define WSA884X_EMEM_54 (WSA884X_DIG_EMEM_BASE + 0x36)
666 #define WSA884X_EMEM_55 (WSA884X_DIG_EMEM_BASE + 0x37)
667 #define WSA884X_EMEM_56 (WSA884X_DIG_EMEM_BASE + 0x38)
668 #define WSA884X_EMEM_57 (WSA884X_DIG_EMEM_BASE + 0x39)
669 #define WSA884X_EMEM_58 (WSA884X_DIG_EMEM_BASE + 0x3a)
670 #define WSA884X_EMEM_59 (WSA884X_DIG_EMEM_BASE + 0x3b)
671 #define WSA884X_EMEM_60 (WSA884X_DIG_EMEM_BASE + 0x3c)
672 #define WSA884X_EMEM_61 (WSA884X_DIG_EMEM_BASE + 0x3d)
673 #define WSA884X_EMEM_62 (WSA884X_DIG_EMEM_BASE + 0x3e)
674 #define WSA884X_EMEM_63 (WSA884X_DIG_EMEM_BASE + 0x3f)
675
676 #define WSA884X_NUM_REGISTERS (WSA884X_EMEM_63 + 1)
677 #define WSA884X_MAX_REGISTER (WSA884X_NUM_REGISTERS - 1)
678
679 #define WSA884X_SUPPLIES_NUM 2
680 #define WSA884X_MAX_SWR_PORTS 6
681 #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
682 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
683 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
684 SNDRV_PCM_RATE_384000)
685 /* Fractional Rates */
686 #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
687 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
688
689 #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
690 SNDRV_PCM_FMTBIT_S24_LE |\
691 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
692
693 struct wsa884x_priv {
694 struct regmap *regmap;
695 struct device *dev;
696 struct regulator_bulk_data supplies[WSA884X_SUPPLIES_NUM];
697 struct sdw_slave *slave;
698 struct sdw_stream_config sconfig;
699 struct sdw_stream_runtime *sruntime;
700 struct sdw_port_config port_config[WSA884X_MAX_SWR_PORTS];
701 struct gpio_desc *sd_n;
702 bool port_prepared[WSA884X_MAX_SWR_PORTS];
703 bool port_enable[WSA884X_MAX_SWR_PORTS];
704 unsigned int variant;
705 int active_ports;
706 int dev_mode;
707 bool hw_init;
708 };
709
710 enum {
711 COMP_OFFSET0,
712 COMP_OFFSET1,
713 COMP_OFFSET2,
714 COMP_OFFSET3,
715 COMP_OFFSET4,
716 };
717
718 enum wsa884x_gain {
719 G_21_DB = 0,
720 G_19P5_DB,
721 G_18_DB,
722 G_16P5_DB,
723 G_15_DB,
724 G_13P5_DB,
725 G_12_DB,
726 G_10P5_DB,
727 G_9_DB,
728 G_7P5_DB,
729 G_6_DB,
730 G_4P5_DB,
731 G_3_DB,
732 G_1P5_DB,
733 G_0_DB,
734 G_M1P5_DB,
735 G_M3_DB,
736 G_M4P5_DB,
737 G_M6_DB,
738 G_MAX_DB,
739 };
740
741 enum wsa884x_isense {
742 ISENSE_6_DB = 0,
743 ISENSE_12_DB,
744 ISENSE_15_DB,
745 ISENSE_18_DB,
746 };
747
748 enum wsa884x_vsense {
749 VSENSE_M12_DB = 0,
750 VSENSE_M15_DB,
751 VSENSE_M18_DB,
752 VSENSE_M21_DB,
753 VSENSE_M24_DB,
754 };
755
756 enum wsa884x_port_ids {
757 WSA884X_PORT_DAC,
758 WSA884X_PORT_COMP,
759 WSA884X_PORT_BOOST,
760 WSA884X_PORT_PBR,
761 WSA884X_PORT_VISENSE,
762 WSA884X_PORT_CPS,
763 };
764
765 static const char * const wsa884x_supply_name[] = {
766 "vdd-io",
767 "vdd-1p8",
768 };
769
770 static const char * const wsa884x_dev_mode_text[] = {
771 "Speaker", "Receiver"
772 };
773
774 enum wsa884x_mode {
775 WSA884X_SPEAKER,
776 WSA884X_RECEIVER,
777 };
778
779 static const struct soc_enum wsa884x_dev_mode_enum =
780 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa884x_dev_mode_text), wsa884x_dev_mode_text);
781
782 static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = {
783 {
784 .num = WSA884X_PORT_DAC + 1,
785 .type = SDW_DPN_SIMPLE,
786 .min_ch = 1,
787 .max_ch = 1,
788 .simple_ch_prep_sm = true,
789 .read_only_wordlength = true,
790 }, {
791 .num = WSA884X_PORT_COMP + 1,
792 .type = SDW_DPN_SIMPLE,
793 .min_ch = 1,
794 .max_ch = 1,
795 .simple_ch_prep_sm = true,
796 .read_only_wordlength = true,
797 }, {
798 .num = WSA884X_PORT_BOOST + 1,
799 .type = SDW_DPN_SIMPLE,
800 .min_ch = 1,
801 .max_ch = 1,
802 .simple_ch_prep_sm = true,
803 .read_only_wordlength = true,
804 }, {
805 .num = WSA884X_PORT_PBR + 1,
806 .type = SDW_DPN_SIMPLE,
807 .min_ch = 1,
808 .max_ch = 1,
809 .simple_ch_prep_sm = true,
810 .read_only_wordlength = true,
811 }, {
812 .num = WSA884X_PORT_VISENSE + 1,
813 .type = SDW_DPN_SIMPLE,
814 .min_ch = 1,
815 .max_ch = 1,
816 .simple_ch_prep_sm = true,
817 .read_only_wordlength = true,
818 }, {
819 .num = WSA884X_PORT_CPS + 1,
820 .type = SDW_DPN_SIMPLE,
821 .min_ch = 1,
822 .max_ch = 1,
823 .simple_ch_prep_sm = true,
824 .read_only_wordlength = true,
825 }
826 };
827
828 static const struct sdw_port_config wsa884x_pconfig[WSA884X_MAX_SWR_PORTS] = {
829 {
830 .num = WSA884X_PORT_DAC + 1,
831 .ch_mask = 0x1,
832 }, {
833 .num = WSA884X_PORT_COMP + 1,
834 .ch_mask = 0xf,
835 }, {
836 .num = WSA884X_PORT_BOOST + 1,
837 .ch_mask = 0x3,
838 }, {
839 .num = WSA884X_PORT_PBR + 1,
840 .ch_mask = 0x1,
841 }, {
842 .num = WSA884X_PORT_VISENSE + 1,
843 .ch_mask = 0x3,
844 }, {
845 .num = WSA884X_PORT_CPS + 1,
846 .ch_mask = 0x3,
847 },
848 };
849
850 static struct reg_default wsa884x_defaults[] = {
851 { WSA884X_BG_CTRL, 0xa5 },
852 { WSA884X_ADC_CTRL, 0x00 },
853 { WSA884X_BOP1_PROG, 0x22 },
854 { WSA884X_BOP2_PROG, 0x44 },
855 { WSA884X_UVLO_PROG, 0x99 },
856 { WSA884X_UVLO_PROG1, 0x70 },
857 { WSA884X_SPARE_CTRL_0, 0x00 },
858 { WSA884X_SPARE_CTRL_1, 0x00 },
859 { WSA884X_SPARE_CTRL_2, 0x00 },
860 { WSA884X_SPARE_CTRL_3, 0x00 },
861 { WSA884X_REF_CTRL, 0xd2 },
862 { WSA884X_BG_TEST_CTL, 0x06 },
863 { WSA884X_BG_BIAS, 0xd7 },
864 { WSA884X_ADC_PROG, 0x08 },
865 { WSA884X_ADC_IREF_CTL, 0x57 },
866 { WSA884X_ADC_ISENS_CTL, 0x47 },
867 { WSA884X_ADC_CLK_CTL, 0x87 },
868 { WSA884X_ADC_TEST_CTL, 0x00 },
869 { WSA884X_ADC_BIAS, 0x51 },
870 { WSA884X_VBAT_SNS, 0xa0 },
871 { WSA884X_BOP_ATEST_SEL, 0x00 },
872 { WSA884X_MISC0, 0x04 },
873 { WSA884X_MISC1, 0x75 },
874 { WSA884X_MISC2, 0x00 },
875 { WSA884X_MISC3, 0x10 },
876 { WSA884X_SPARE_TSBG_0, 0x00 },
877 { WSA884X_SPARE_TUNE_0, 0x00 },
878 { WSA884X_SPARE_TUNE_1, 0x00 },
879 { WSA884X_VSENSE1, 0xe7 },
880 { WSA884X_ISENSE2, 0x27 },
881 { WSA884X_SPARE_CTL_1, 0x00 },
882 { WSA884X_SPARE_CTL_2, 0x00 },
883 { WSA884X_SPARE_CTL_3, 0x00 },
884 { WSA884X_SPARE_CTL_4, 0x00 },
885 { WSA884X_EN, 0x10 },
886 { WSA884X_OVERRIDE1, 0x00 },
887 { WSA884X_OVERRIDE2, 0x08 },
888 { WSA884X_ISENSE1, 0xd4 },
889 { WSA884X_ISENSE_CAL, 0x00 },
890 { WSA884X_MISC, 0x00 },
891 { WSA884X_ADC_0, 0x00 },
892 { WSA884X_ADC_1, 0x00 },
893 { WSA884X_ADC_2, 0x40 },
894 { WSA884X_ADC_3, 0x80 },
895 { WSA884X_ADC_4, 0x25 },
896 { WSA884X_ADC_5, 0x24 },
897 { WSA884X_ADC_6, 0x0a },
898 { WSA884X_ADC_7, 0x81 },
899 { WSA884X_IVSENSE_SPARE_TUNE_1, 0x00 },
900 { WSA884X_SPARE_TUNE_2, 0x00 },
901 { WSA884X_SPARE_TUNE_3, 0x00 },
902 { WSA884X_SPARE_TUNE_4, 0x00 },
903 { WSA884X_TOP_CTRL1, 0xd3 },
904 { WSA884X_CLIP_DET_CTRL1, 0x7e },
905 { WSA884X_CLIP_DET_CTRL2, 0x4c },
906 { WSA884X_DAC_CTRL1, 0xa4 },
907 { WSA884X_DAC_VCM_CTRL_REG1, 0x02 },
908 { WSA884X_DAC_VCM_CTRL_REG2, 0x00 },
909 { WSA884X_DAC_VCM_CTRL_REG3, 0x00 },
910 { WSA884X_DAC_VCM_CTRL_REG4, 0x00 },
911 { WSA884X_DAC_VCM_CTRL_REG5, 0x00 },
912 { WSA884X_DAC_VCM_CTRL_REG6, 0x00 },
913 { WSA884X_PWM_CLK_CTL, 0x20 },
914 { WSA884X_DRV_LF_LDO_SEL, 0xaa },
915 { WSA884X_OCP_CTL, 0xc6 },
916 { WSA884X_PDRV_HS_CTL, 0x52 },
917 { WSA884X_PDRV_LS_CTL, 0x4a },
918 { WSA884X_SPK_TOP_SPARE_CTL_1, 0x00 },
919 { WSA884X_SPK_TOP_SPARE_CTL_2, 0x00 },
920 { WSA884X_SPK_TOP_SPARE_CTL_3, 0x00 },
921 { WSA884X_SPK_TOP_SPARE_CTL_4, 0x00 },
922 { WSA884X_SPARE_CTL_5, 0x00 },
923 { WSA884X_DAC_EN_DEBUG_REG, 0x00 },
924 { WSA884X_DAC_OPAMP_BIAS1_REG, 0x48 },
925 { WSA884X_DAC_OPAMP_BIAS2_REG, 0x48 },
926 { WSA884X_DAC_TUNE1, 0x02 },
927 { WSA884X_DAC_VOLTAGE_CTRL_REG, 0x05 },
928 { WSA884X_ATEST1_REG, 0x00 },
929 { WSA884X_ATEST2_REG, 0x00 },
930 { WSA884X_TOP_BIAS_REG1, 0x6a },
931 { WSA884X_TOP_BIAS_REG2, 0x65 },
932 { WSA884X_TOP_BIAS_REG3, 0x55 },
933 { WSA884X_TOP_BIAS_REG4, 0xa9 },
934 { WSA884X_PWRSTG_DBG2, 0x21 },
935 { WSA884X_DRV_LF_BLK_EN, 0x0f },
936 { WSA884X_DRV_LF_EN, 0x0a },
937 { WSA884X_DRV_LF_MASK_DCC_CTL, 0x08 },
938 { WSA884X_DRV_LF_MISC_CTL1, 0x30 },
939 { WSA884X_DRV_LF_REG_GAIN, 0x00 },
940 { WSA884X_DRV_OS_CAL_CTL, 0x00 },
941 { WSA884X_DRV_OS_CAL_CTL1, 0x90 },
942 { WSA884X_PWRSTG_DBG, 0x08 },
943 { WSA884X_BBM_CTL, 0x92 },
944 { WSA884X_TOP_MISC1, 0x00 },
945 { WSA884X_DAC_VCM_CTRL_REG7, 0x00 },
946 { WSA884X_TOP_BIAS_REG5, 0x15 },
947 { WSA884X_DRV_LF_MISC_CTL2, 0x00 },
948 { WSA884X_STB_CTRL1, 0x42 },
949 { WSA884X_CURRENT_LIMIT, 0x54 },
950 { WSA884X_BYP_CTRL1, 0x01 },
951 { WSA884X_SPARE_CTL_0, 0x00 },
952 { WSA884X_BOOST_SPARE_CTL_1, 0x00 },
953 { WSA884X_IBIAS1, 0x00 },
954 { WSA884X_IBIAS2, 0x00 },
955 { WSA884X_IBIAS3, 0x00 },
956 { WSA884X_EN_CTRL, 0x42 },
957 { WSA884X_STB_CTRL2, 0x03 },
958 { WSA884X_STB_CTRL3, 0x3c },
959 { WSA884X_STB_CTRL4, 0x30 },
960 { WSA884X_BYP_CTRL2, 0x97 },
961 { WSA884X_BYP_CTRL3, 0x11 },
962 { WSA884X_ZX_CTRL1, 0xf0 },
963 { WSA884X_ZX_CTRL2, 0x04 },
964 { WSA884X_BLEEDER_CTRL, 0x04 },
965 { WSA884X_BOOST_MISC, 0x62 },
966 { WSA884X_PWRSTAGE_CTRL1, 0x00 },
967 { WSA884X_PWRSTAGE_CTRL2, 0x31 },
968 { WSA884X_PWRSTAGE_CTRL3, 0x81 },
969 { WSA884X_PWRSTAGE_CTRL4, 0x5f },
970 { WSA884X_MAXD_REG1, 0x00 },
971 { WSA884X_MAXD_REG2, 0x5b },
972 { WSA884X_ILIM_CTRL1, 0xe2 },
973 { WSA884X_ILIM_CTRL2, 0x90 },
974 { WSA884X_TEST_CTRL1, 0x00 },
975 { WSA884X_TEST_CTRL2, 0x00 },
976 { WSA884X_SPARE1, 0x00 },
977 { WSA884X_BOOT_CAP_CHECK, 0x01 },
978 { WSA884X_PON_CTL_0, 0x12 },
979 { WSA884X_PWRSAV_CTL, 0xaa },
980 { WSA884X_PON_LDOL_SPARE_CTL_0, 0x00 },
981 { WSA884X_PON_LDOL_SPARE_CTL_1, 0x00 },
982 { WSA884X_PON_LDOL_SPARE_CTL_2, 0x00 },
983 { WSA884X_PON_LDOL_SPARE_CTL_3, 0x00 },
984 { WSA884X_PON_CLT_1, 0xe1 },
985 { WSA884X_PON_CTL_2, 0x00 },
986 { WSA884X_PON_CTL_3, 0x70 },
987 { WSA884X_CKWD_CTL_0, 0x14 },
988 { WSA884X_CKWD_CTL_1, 0x3b },
989 { WSA884X_CKWD_CTL_2, 0x00 },
990 { WSA884X_CKSK_CTL_0, 0x00 },
991 { WSA884X_PADSW_CTL_0, 0x00 },
992 { WSA884X_TEST_0, 0x00 },
993 { WSA884X_TEST_1, 0x00 },
994 { WSA884X_PON_LDOL_SPARE_TUNE_0, 0x00 },
995 { WSA884X_PON_LDOL_SPARE_TUNE_1, 0x00 },
996 { WSA884X_PON_LDOL_SPARE_TUNE_2, 0x00 },
997 { WSA884X_PON_LDOL_SPARE_TUNE_3, 0x00 },
998 { WSA884X_PON_LDOL_SPARE_TUNE_4, 0x00 },
999 { WSA884X_DIG_CTRL0_PAGE, 0x00 },
1000 { WSA884X_CDC_RST_CTL, 0x01 },
1001 { WSA884X_SWR_RESET_EN, 0x00 },
1002 { WSA884X_TOP_CLK_CFG, 0x00 },
1003 { WSA884X_SWR_CLK_RATE, 0x00 },
1004 { WSA884X_CDC_PATH_MODE, 0x00 },
1005 { WSA884X_CDC_CLK_CTL, 0x1f },
1006 { WSA884X_PA_FSM_EN, 0x00 },
1007 { WSA884X_PA_FSM_CTL0, 0x00 },
1008 { WSA884X_PA_FSM_CTL1, 0xfe },
1009 { WSA884X_PA_FSM_TIMER0, 0x80 },
1010 { WSA884X_PA_FSM_TIMER1, 0x80 },
1011 { WSA884X_PA_FSM_ERR_CTL, 0x00 },
1012 { WSA884X_PA_FSM_MSK0, 0x00 },
1013 { WSA884X_PA_FSM_MSK1, 0x00 },
1014 { WSA884X_PA_FSM_BYP_CTL, 0x00 },
1015 { WSA884X_PA_FSM_BYP0, 0x00 },
1016 { WSA884X_PA_FSM_BYP1, 0x00 },
1017 { WSA884X_TADC_VALUE_CTL, 0x03 },
1018 { WSA884X_TEMP_DETECT_CTL, 0x01 },
1019 { WSA884X_TEMP_CONFIG0, 0x00 },
1020 { WSA884X_TEMP_CONFIG1, 0x00 },
1021 { WSA884X_VBAT_THRM_FLT_CTL, 0x7f },
1022 { WSA884X_VBAT_CAL_CTL, 0x01 },
1023 { WSA884X_UVLO_DEGLITCH_CTL, 0x05 },
1024 { WSA884X_BOP_DEGLITCH_CTL, 0x05 },
1025 { WSA884X_VBAT_ZONE_DETC_CTL, 0x31 },
1026 { WSA884X_CPS_CTL, 0x00 },
1027 { WSA884X_CDC_RX_CTL, 0xfe },
1028 { WSA884X_CDC_SPK_DSM_A1_0, 0x00 },
1029 { WSA884X_CDC_SPK_DSM_A1_1, 0x01 },
1030 { WSA884X_CDC_SPK_DSM_A2_0, 0x96 },
1031 { WSA884X_CDC_SPK_DSM_A2_1, 0x09 },
1032 { WSA884X_CDC_SPK_DSM_A3_0, 0xab },
1033 { WSA884X_CDC_SPK_DSM_A3_1, 0x05 },
1034 { WSA884X_CDC_SPK_DSM_A4_0, 0x1c },
1035 { WSA884X_CDC_SPK_DSM_A4_1, 0x02 },
1036 { WSA884X_CDC_SPK_DSM_A5_0, 0x17 },
1037 { WSA884X_CDC_SPK_DSM_A5_1, 0x02 },
1038 { WSA884X_CDC_SPK_DSM_A6_0, 0xaa },
1039 { WSA884X_CDC_SPK_DSM_A7_0, 0xe3 },
1040 { WSA884X_CDC_SPK_DSM_C_0, 0x69 },
1041 { WSA884X_CDC_SPK_DSM_C_1, 0x54 },
1042 { WSA884X_CDC_SPK_DSM_C_2, 0x02 },
1043 { WSA884X_CDC_SPK_DSM_C_3, 0x15 },
1044 { WSA884X_CDC_SPK_DSM_R1, 0xa4 },
1045 { WSA884X_CDC_SPK_DSM_R2, 0xb5 },
1046 { WSA884X_CDC_SPK_DSM_R3, 0x86 },
1047 { WSA884X_CDC_SPK_DSM_R4, 0x85 },
1048 { WSA884X_CDC_SPK_DSM_R5, 0xaa },
1049 { WSA884X_CDC_SPK_DSM_R6, 0xe2 },
1050 { WSA884X_CDC_SPK_DSM_R7, 0x62 },
1051 { WSA884X_CDC_SPK_GAIN_PDM_0, 0x00 },
1052 { WSA884X_CDC_SPK_GAIN_PDM_1, 0xfc },
1053 { WSA884X_CDC_SPK_GAIN_PDM_2, 0x05 },
1054 { WSA884X_PDM_WD_CTL, 0x00 },
1055 { WSA884X_DEM_BYPASS_DATA0, 0x00 },
1056 { WSA884X_DEM_BYPASS_DATA1, 0x00 },
1057 { WSA884X_DEM_BYPASS_DATA2, 0x00 },
1058 { WSA884X_DEM_BYPASS_DATA3, 0x00 },
1059 { WSA884X_DRE_CTL_0, 0x70 },
1060 { WSA884X_DRE_CTL_1, 0x04 },
1061 { WSA884X_DRE_IDLE_DET_CTL, 0x2f },
1062 { WSA884X_GAIN_RAMPING_CTL, 0x50 },
1063 { WSA884X_GAIN_RAMPING_MIN, 0x12 },
1064 { WSA884X_TAGC_CTL, 0x15 },
1065 { WSA884X_TAGC_TIME, 0xbc },
1066 { WSA884X_TAGC_FORCE_VAL, 0x00 },
1067 { WSA884X_VAGC_CTL, 0x01 },
1068 { WSA884X_VAGC_TIME, 0x0f },
1069 { WSA884X_VAGC_ATTN_LVL_1, 0x03 },
1070 { WSA884X_VAGC_ATTN_LVL_2, 0x06 },
1071 { WSA884X_VAGC_ATTN_LVL_3, 0x09 },
1072 { WSA884X_CLSH_CTL_0, 0x37 },
1073 { WSA884X_CLSH_CTL_1, 0x81 },
1074 { WSA884X_CLSH_V_HD_PA, 0x0c },
1075 { WSA884X_CLSH_V_PA_MIN, 0x00 },
1076 { WSA884X_CLSH_OVRD_VAL, 0x00 },
1077 { WSA884X_CLSH_HARD_MAX, 0xff },
1078 { WSA884X_CLSH_SOFT_MAX, 0xf5 },
1079 { WSA884X_CLSH_SIG_DP, 0x00 },
1080 { WSA884X_PBR_DELAY_CTL, 0x07 },
1081 { WSA884X_CLSH_SRL_MAX_PBR, 0x02 },
1082 { WSA884X_CLSH_VTH1, 0x00 },
1083 { WSA884X_CLSH_VTH2, 0x00 },
1084 { WSA884X_CLSH_VTH3, 0x00 },
1085 { WSA884X_CLSH_VTH4, 0x00 },
1086 { WSA884X_CLSH_VTH5, 0x00 },
1087 { WSA884X_CLSH_VTH6, 0x00 },
1088 { WSA884X_CLSH_VTH7, 0x00 },
1089 { WSA884X_CLSH_VTH8, 0x00 },
1090 { WSA884X_CLSH_VTH9, 0x00 },
1091 { WSA884X_CLSH_VTH10, 0x00 },
1092 { WSA884X_CLSH_VTH11, 0x00 },
1093 { WSA884X_CLSH_VTH12, 0x00 },
1094 { WSA884X_CLSH_VTH13, 0x00 },
1095 { WSA884X_CLSH_VTH14, 0x00 },
1096 { WSA884X_CLSH_VTH15, 0x00 },
1097 { WSA884X_DIG_CTRL1_PAGE, 0x00 },
1098 { WSA884X_PIN_CTL, 0x04 },
1099 { WSA884X_PIN_CTL_OE, 0x00 },
1100 { WSA884X_PIN_WDATA_IOPAD, 0x00 },
1101 { WSA884X_I2C_SLAVE_CTL, 0x00 },
1102 { WSA884X_SPMI_PAD_CTL0, 0x2f },
1103 { WSA884X_SPMI_PAD_CTL1, 0x2f },
1104 { WSA884X_SPMI_PAD_CTL2, 0x2f },
1105 { WSA884X_MEM_CTL, 0x00 },
1106 { WSA884X_SWR_HM_TEST0, 0x08 },
1107 { WSA884X_OTP_CTRL0, 0x00 },
1108 { WSA884X_OTP_CTRL2, 0x00 },
1109 { WSA884X_OTP_PRG_TCSP0, 0x77 },
1110 { WSA884X_OTP_PRG_TCSP1, 0x00 },
1111 { WSA884X_OTP_PRG_TPPS, 0x47 },
1112 { WSA884X_OTP_PRG_TVPS, 0x3b },
1113 { WSA884X_OTP_PRG_TVPH, 0x47 },
1114 { WSA884X_OTP_PRG_TPPR0, 0x47 },
1115 { WSA884X_OTP_PRG_TPPR1, 0x00 },
1116 { WSA884X_OTP_PRG_TPPH, 0x47 },
1117 { WSA884X_OTP_PRG_END, 0x47 },
1118 { WSA884X_WAVG_PLAY, 0x00 },
1119 { WSA884X_WAVG_CTL, 0x06 },
1120 { WSA884X_WAVG_LRA_PER_0, 0xd1 },
1121 { WSA884X_WAVG_LRA_PER_1, 0x00 },
1122 { WSA884X_WAVG_DELTA_THETA_0, 0xe6 },
1123 { WSA884X_WAVG_DELTA_THETA_1, 0x04 },
1124 { WSA884X_WAVG_DIRECT_AMP_0, 0x50 },
1125 { WSA884X_WAVG_DIRECT_AMP_1, 0x00 },
1126 { WSA884X_WAVG_PTRN_AMP0_0, 0x50 },
1127 { WSA884X_WAVG_PTRN_AMP0_1, 0x00 },
1128 { WSA884X_WAVG_PTRN_AMP1_0, 0x50 },
1129 { WSA884X_WAVG_PTRN_AMP1_1, 0x00 },
1130 { WSA884X_WAVG_PTRN_AMP2_0, 0x50 },
1131 { WSA884X_WAVG_PTRN_AMP2_1, 0x00 },
1132 { WSA884X_WAVG_PTRN_AMP3_0, 0x50 },
1133 { WSA884X_WAVG_PTRN_AMP3_1, 0x00 },
1134 { WSA884X_WAVG_PTRN_AMP4_0, 0x50 },
1135 { WSA884X_WAVG_PTRN_AMP4_1, 0x00 },
1136 { WSA884X_WAVG_PTRN_AMP5_0, 0x50 },
1137 { WSA884X_WAVG_PTRN_AMP5_1, 0x00 },
1138 { WSA884X_WAVG_PTRN_AMP6_0, 0x50 },
1139 { WSA884X_WAVG_PTRN_AMP6_1, 0x00 },
1140 { WSA884X_WAVG_PTRN_AMP7_0, 0x50 },
1141 { WSA884X_WAVG_PTRN_AMP7_1, 0x00 },
1142 { WSA884X_WAVG_PER_0_1, 0x88 },
1143 { WSA884X_WAVG_PER_2_3, 0x88 },
1144 { WSA884X_WAVG_PER_4_5, 0x88 },
1145 { WSA884X_WAVG_PER_6_7, 0x88 },
1146 { WSA884X_INTR_MODE, 0x00 },
1147 { WSA884X_INTR_MASK0, 0x90 },
1148 { WSA884X_INTR_MASK1, 0x00 },
1149 { WSA884X_INTR_CLEAR0, 0x00 },
1150 { WSA884X_INTR_CLEAR1, 0x00 },
1151 { WSA884X_INTR_LEVEL0, 0x04 },
1152 { WSA884X_INTR_LEVEL1, 0x00 },
1153 { WSA884X_INTR_SET0, 0x00 },
1154 { WSA884X_INTR_SET1, 0x00 },
1155 { WSA884X_INTR_TEST0, 0x00 },
1156 { WSA884X_INTR_TEST1, 0x00 },
1157 { WSA884X_PDM_TEST_MODE, 0x00 },
1158 { WSA884X_PA_FSM_DBG, 0x00 },
1159 { WSA884X_DIG_DEBUG_MODE, 0x00 },
1160 { WSA884X_DIG_DEBUG_SEL, 0x00 },
1161 { WSA884X_DIG_DEBUG_EN, 0x00 },
1162 { WSA884X_TADC_DETECT_DBG_CTL, 0x00 },
1163 { WSA884X_TADC_DEBUG_MSB, 0x00 },
1164 { WSA884X_TADC_DEBUG_LSB, 0x00 },
1165 { WSA884X_SAMPLE_EDGE_SEL, 0x7f },
1166 { WSA884X_SWR_EDGE_SEL, 0x00 },
1167 { WSA884X_TEST_MODE_CTL, 0x05 },
1168 { WSA884X_IOPAD_CTL, 0x00 },
1169 { WSA884X_ANA_CSR_DBG_ADD, 0x00 },
1170 { WSA884X_ANA_CSR_DBG_CTL, 0x12 },
1171 { WSA884X_CLK_DBG_CTL, 0x00 },
1172 { WSA884X_SPARE_0, 0x00 },
1173 { WSA884X_SPARE_1, 0x00 },
1174 { WSA884X_SPARE_2, 0x00 },
1175 { WSA884X_SCODE, 0x00 },
1176 { WSA884X_DIG_TRIM_PAGE, 0x00 },
1177 { WSA884X_EMEM_0, 0x00 },
1178 { WSA884X_EMEM_1, 0x00 },
1179 { WSA884X_EMEM_2, 0x00 },
1180 { WSA884X_EMEM_3, 0x00 },
1181 { WSA884X_EMEM_4, 0x00 },
1182 { WSA884X_EMEM_5, 0x00 },
1183 { WSA884X_EMEM_6, 0x00 },
1184 { WSA884X_EMEM_7, 0x00 },
1185 { WSA884X_EMEM_8, 0x00 },
1186 { WSA884X_EMEM_9, 0x00 },
1187 { WSA884X_EMEM_10, 0x00 },
1188 { WSA884X_EMEM_11, 0x00 },
1189 { WSA884X_EMEM_12, 0x00 },
1190 { WSA884X_EMEM_13, 0x00 },
1191 { WSA884X_EMEM_14, 0x00 },
1192 { WSA884X_EMEM_15, 0x00 },
1193 { WSA884X_EMEM_16, 0x00 },
1194 { WSA884X_EMEM_17, 0x00 },
1195 { WSA884X_EMEM_18, 0x00 },
1196 { WSA884X_EMEM_19, 0x00 },
1197 { WSA884X_EMEM_20, 0x00 },
1198 { WSA884X_EMEM_21, 0x00 },
1199 { WSA884X_EMEM_22, 0x00 },
1200 { WSA884X_EMEM_23, 0x00 },
1201 { WSA884X_EMEM_24, 0x00 },
1202 { WSA884X_EMEM_25, 0x00 },
1203 { WSA884X_EMEM_26, 0x00 },
1204 { WSA884X_EMEM_27, 0x00 },
1205 { WSA884X_EMEM_28, 0x00 },
1206 { WSA884X_EMEM_29, 0x00 },
1207 { WSA884X_EMEM_30, 0x00 },
1208 { WSA884X_EMEM_31, 0x00 },
1209 { WSA884X_EMEM_32, 0x00 },
1210 { WSA884X_EMEM_33, 0x00 },
1211 { WSA884X_EMEM_34, 0x00 },
1212 { WSA884X_EMEM_35, 0x00 },
1213 { WSA884X_EMEM_36, 0x00 },
1214 { WSA884X_EMEM_37, 0x00 },
1215 { WSA884X_EMEM_38, 0x00 },
1216 { WSA884X_EMEM_39, 0x00 },
1217 { WSA884X_EMEM_40, 0x00 },
1218 { WSA884X_EMEM_41, 0x00 },
1219 { WSA884X_EMEM_42, 0x00 },
1220 { WSA884X_EMEM_43, 0x00 },
1221 { WSA884X_EMEM_44, 0x00 },
1222 { WSA884X_EMEM_45, 0x00 },
1223 { WSA884X_EMEM_46, 0x00 },
1224 { WSA884X_EMEM_47, 0x00 },
1225 { WSA884X_EMEM_48, 0x00 },
1226 { WSA884X_EMEM_49, 0x00 },
1227 { WSA884X_EMEM_50, 0x00 },
1228 { WSA884X_EMEM_51, 0x00 },
1229 { WSA884X_EMEM_52, 0x00 },
1230 { WSA884X_EMEM_53, 0x00 },
1231 { WSA884X_EMEM_54, 0x00 },
1232 { WSA884X_EMEM_55, 0x00 },
1233 { WSA884X_EMEM_56, 0x00 },
1234 { WSA884X_EMEM_57, 0x00 },
1235 { WSA884X_EMEM_58, 0x00 },
1236 { WSA884X_EMEM_59, 0x00 },
1237 { WSA884X_EMEM_60, 0x00 },
1238 { WSA884X_EMEM_61, 0x00 },
1239 { WSA884X_EMEM_62, 0x00 },
1240 { WSA884X_EMEM_63, 0x00 },
1241 };
1242
wsa884x_readonly_register(struct device * dev,unsigned int reg)1243 static bool wsa884x_readonly_register(struct device *dev, unsigned int reg)
1244 {
1245 switch (reg) {
1246 case WSA884X_DOUT_MSB:
1247 case WSA884X_DOUT_LSB:
1248 case WSA884X_STATUS:
1249 case WSA884X_SPK_TOP_SPARE_TUNE_2:
1250 case WSA884X_SPK_TOP_SPARE_TUNE_3:
1251 case WSA884X_SPK_TOP_SPARE_TUNE_4:
1252 case WSA884X_SPARE_TUNE_5:
1253 case WSA884X_SPARE_TUNE_6:
1254 case WSA884X_SPARE_TUNE_7:
1255 case WSA884X_SPARE_TUNE_8:
1256 case WSA884X_SPARE_TUNE_9:
1257 case WSA884X_SPARE_TUNE_10:
1258 case WSA884X_PA_STATUS0:
1259 case WSA884X_PA_STATUS1:
1260 case WSA884X_PA_STATUS2:
1261 case WSA884X_PA_STATUS3:
1262 case WSA884X_PA_STATUS4:
1263 case WSA884X_PA_STATUS5:
1264 case WSA884X_SPARE_RO_1:
1265 case WSA884X_SPARE_RO_2:
1266 case WSA884X_SPARE_RO_3:
1267 case WSA884X_SPARE_RO_0:
1268 case WSA884X_BOOST_SPARE_RO_1:
1269 case WSA884X_STATUS_0:
1270 case WSA884X_STATUS_1:
1271 case WSA884X_CHIP_ID0:
1272 case WSA884X_CHIP_ID1:
1273 case WSA884X_CHIP_ID2:
1274 case WSA884X_CHIP_ID3:
1275 case WSA884X_BUS_ID:
1276 case WSA884X_PA_FSM_STA0:
1277 case WSA884X_PA_FSM_STA1:
1278 case WSA884X_PA_FSM_ERR_COND0:
1279 case WSA884X_PA_FSM_ERR_COND1:
1280 case WSA884X_TEMP_DIN_MSB:
1281 case WSA884X_TEMP_DIN_LSB:
1282 case WSA884X_TEMP_DOUT_MSB:
1283 case WSA884X_TEMP_DOUT_LSB:
1284 case WSA884X_VBAT_DIN_MSB:
1285 case WSA884X_VBAT_DIN_LSB:
1286 case WSA884X_VBAT_DOUT_MSB:
1287 case WSA884X_VBAT_DOUT_LSB:
1288 case WSA884X_VBAT_CAL_MSB:
1289 case WSA884X_VBAT_CAL_LSB:
1290 case WSA884X_VPHX_SYS_EN_STATUS:
1291 case WSA884X_PIN_STATUS:
1292 case WSA884X_SWR_HM_TEST1:
1293 case WSA884X_OTP_CTRL1:
1294 case WSA884X_OTP_STAT:
1295 case WSA884X_WAVG_STA:
1296 case WSA884X_INTR_STATUS0:
1297 case WSA884X_INTR_STATUS1:
1298 case WSA884X_ATE_TEST_MODE:
1299 case WSA884X_SPARE_R:
1300 return true;
1301 }
1302 return false;
1303 }
1304
wsa884x_writeable_register(struct device * dev,unsigned int reg)1305 static bool wsa884x_writeable_register(struct device *dev, unsigned int reg)
1306 {
1307 return !wsa884x_readonly_register(dev, reg);
1308 }
1309
wsa884x_volatile_register(struct device * dev,unsigned int reg)1310 static bool wsa884x_volatile_register(struct device *dev, unsigned int reg)
1311 {
1312 switch (reg) {
1313 case WSA884X_ANA_WO_CTL_0:
1314 case WSA884X_ANA_WO_CTL_1:
1315 return true;
1316 }
1317 return wsa884x_readonly_register(dev, reg);
1318 }
1319
1320 static struct regmap_config wsa884x_regmap_config = {
1321 .reg_bits = 32,
1322 .val_bits = 8,
1323 .cache_type = REGCACHE_MAPLE,
1324 .reg_defaults = wsa884x_defaults,
1325 .max_register = WSA884X_MAX_REGISTER,
1326 .num_reg_defaults = ARRAY_SIZE(wsa884x_defaults),
1327 .volatile_reg = wsa884x_volatile_register,
1328 .writeable_reg = wsa884x_writeable_register,
1329 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
1330 .val_format_endian = REGMAP_ENDIAN_NATIVE,
1331 .use_single_read = true,
1332 };
1333
1334 static const struct reg_sequence wsa884x_reg_init[] = {
1335 { WSA884X_BOP2_PROG, FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_VTH_MASK, 0x6) |
1336 FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_HYST_MASK, 0x6) },
1337 { WSA884X_REF_CTRL, (0xd2 & ~WSA884X_REF_CTRL_BG_RDY_SEL_MASK) |
1338 FIELD_PREP_CONST(WSA884X_REF_CTRL_BG_RDY_SEL_MASK, 0x1) },
1339 /*
1340 * Downstream suggests for batteries different than 1-Stacked (1S):
1341 * { WSA884X_TOP_CTRL1, 0xd3 & ~WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK },
1342 */
1343 { WSA884X_STB_CTRL1, (0x42 & ~WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK) |
1344 FIELD_PREP_CONST(WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK, 0xd) },
1345 { WSA884X_CURRENT_LIMIT, (0x54 & ~WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK) |
1346 FIELD_PREP_CONST(WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK, 0x9) },
1347 { WSA884X_ZX_CTRL1, (0xf0 & ~WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK) |
1348 FIELD_PREP_CONST(WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK, 0x3) },
1349 { WSA884X_ILIM_CTRL1, (0xe2 & ~WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK) |
1350 FIELD_PREP_CONST(WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK, 0x3) },
1351 { WSA884X_CKWD_CTL_1, FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK, 0x0) |
1352 FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK, 0x13) },
1353 { WSA884X_PA_FSM_CTL1, (0xfe & ~WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK) |
1354 FIELD_PREP_CONST(WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK, 0x4) }, /* == 0xfe */
1355 { WSA884X_VBAT_THRM_FLT_CTL, (0x7f & ~WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK) |
1356 FIELD_PREP_CONST(WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK, 0x4) },
1357 { WSA884X_VBAT_CAL_CTL, FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_RESERVE_MASK, 0x2) |
1358 FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK, 0x1) },
1359 { WSA884X_BOP_DEGLITCH_CTL, FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK, 0x8) |
1360 FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK, 0x1) },
1361 { WSA884X_CDC_SPK_DSM_A2_0, 0x0a },
1362 { WSA884X_CDC_SPK_DSM_A2_1, 0x08 },
1363 { WSA884X_CDC_SPK_DSM_A3_0, 0xf3 },
1364 { WSA884X_CDC_SPK_DSM_A3_1, 0x07 },
1365 { WSA884X_CDC_SPK_DSM_A4_0, 0x79 },
1366 { WSA884X_CDC_SPK_DSM_A5_0, 0x0b },
1367 { WSA884X_CDC_SPK_DSM_A6_0, 0x8a },
1368 { WSA884X_CDC_SPK_DSM_A7_0, 0x9b },
1369 { WSA884X_CDC_SPK_DSM_C_0, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK, 0x6) |
1370 FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK, 0x8) },
1371 { WSA884X_CDC_SPK_DSM_C_2, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK, 0xf) },
1372 { WSA884X_CDC_SPK_DSM_C_3, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK, 0x20) },
1373 { WSA884X_CDC_SPK_DSM_R1, 0x83 },
1374 { WSA884X_CDC_SPK_DSM_R2, 0x7f },
1375 { WSA884X_CDC_SPK_DSM_R3, 0x9d },
1376 { WSA884X_CDC_SPK_DSM_R4, 0x82 },
1377 { WSA884X_CDC_SPK_DSM_R5, 0x8b },
1378 { WSA884X_CDC_SPK_DSM_R6, 0x9b },
1379 { WSA884X_CDC_SPK_DSM_R7, 0x3f },
1380 /* Speaker mode by default */
1381 { WSA884X_DRE_CTL_0, FIELD_PREP_CONST(WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x7) },
1382 { WSA884X_CLSH_CTL_0, (0x37 & ~WSA884X_CLSH_CTL_0_DLY_CODE_MASK) |
1383 FIELD_PREP_CONST(WSA884X_CLSH_CTL_0_DLY_CODE_MASK, 0x6) },
1384 /*
1385 * WSA884X_CLSH_VTH values for speaker mode with G_21_DB system gain,
1386 * battery 1S and rload 8 Ohms.
1387 */
1388 { WSA884X_CLSH_VTH1, WSA884X_VTH_TO_REG(863), },
1389 { WSA884X_CLSH_VTH2, WSA884X_VTH_TO_REG(918), },
1390 { WSA884X_CLSH_VTH3, WSA884X_VTH_TO_REG(980), },
1391 { WSA884X_CLSH_VTH4, WSA884X_VTH_TO_REG(1043), },
1392 { WSA884X_CLSH_VTH5, WSA884X_VTH_TO_REG(1098), },
1393 { WSA884X_CLSH_VTH6, WSA884X_VTH_TO_REG(1137), },
1394 { WSA884X_CLSH_VTH7, WSA884X_VTH_TO_REG(1184), },
1395 { WSA884X_CLSH_VTH8, WSA884X_VTH_TO_REG(1239), },
1396 { WSA884X_CLSH_VTH9, WSA884X_VTH_TO_REG(1278), },
1397 { WSA884X_CLSH_VTH10, WSA884X_VTH_TO_REG(1380), },
1398 { WSA884X_CLSH_VTH11, WSA884X_VTH_TO_REG(1482), },
1399 { WSA884X_CLSH_VTH12, WSA884X_VTH_TO_REG(1584), },
1400 { WSA884X_CLSH_VTH13, WSA884X_VTH_TO_REG(1663), },
1401 { WSA884X_CLSH_VTH14, WSA884X_VTH_TO_REG(1780), },
1402 { WSA884X_CLSH_VTH15, WSA884X_VTH_TO_REG(2000), },
1403 { WSA884X_ANA_WO_CTL_1, 0x00 },
1404 { WSA884X_OTP_REG_38, 0x00 },
1405 { WSA884X_OTP_REG_40, FIELD_PREP_CONST(WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK, 0x8) },
1406 };
1407
wsa884x_set_gain_parameters(struct wsa884x_priv * wsa884x)1408 static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x)
1409 {
1410 struct regmap *regmap = wsa884x->regmap;
1411 unsigned int min_gain, igain, vgain, comp_offset;
1412
1413 /*
1414 * Downstream sets gain parameters customized per boards per use-case.
1415 * Choose here some sane values matching knowon users, like QRD8550
1416 * board:.
1417 *
1418 * Values match here downstream:
1419 * For WSA884X_RECEIVER - G_7P5_DB system gain
1420 * For WSA884X_SPEAKER - G_21_DB system gain
1421 */
1422 if (wsa884x->dev_mode == WSA884X_RECEIVER) {
1423 comp_offset = COMP_OFFSET4;
1424 min_gain = G_M6_DB;
1425 igain = ISENSE_18_DB;
1426 vgain = VSENSE_M12_DB;
1427 } else {
1428 /* WSA884X_SPEAKER */
1429 comp_offset = COMP_OFFSET0;
1430 min_gain = G_0_DB;
1431 igain = ISENSE_12_DB;
1432 vgain = VSENSE_M24_DB;
1433 }
1434
1435 regmap_update_bits(regmap, WSA884X_ISENSE2,
1436 WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK,
1437 FIELD_PREP(WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK, igain));
1438 regmap_update_bits(regmap, WSA884X_VSENSE1,
1439 WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK,
1440 FIELD_PREP(WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK, vgain));
1441 regmap_update_bits(regmap, WSA884X_GAIN_RAMPING_MIN,
1442 WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK,
1443 FIELD_PREP(WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK, min_gain));
1444
1445 if (wsa884x->port_enable[WSA884X_PORT_COMP]) {
1446 regmap_update_bits(regmap, WSA884X_DRE_CTL_0,
1447 WSA884X_DRE_CTL_0_OFFSET_MASK,
1448 FIELD_PREP(WSA884X_DRE_CTL_0_OFFSET_MASK, comp_offset));
1449
1450 regmap_update_bits(regmap, WSA884X_DRE_CTL_1,
1451 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1452 FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x0));
1453 } else {
1454 regmap_update_bits(regmap, WSA884X_DRE_CTL_1,
1455 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1456 FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x1));
1457 }
1458 }
1459
wsa884x_init(struct wsa884x_priv * wsa884x)1460 static void wsa884x_init(struct wsa884x_priv *wsa884x)
1461 {
1462 unsigned int wo_ctl_0;
1463 unsigned int variant = 0;
1464
1465 if (!regmap_read(wsa884x->regmap, WSA884X_OTP_REG_0, &variant))
1466 wsa884x->variant = variant & WSA884X_OTP_REG_0_ID_MASK;
1467
1468 regmap_multi_reg_write(wsa884x->regmap, wsa884x_reg_init,
1469 ARRAY_SIZE(wsa884x_reg_init));
1470
1471 wo_ctl_0 = 0xc;
1472 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK,
1473 WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER);
1474 /* Assume that compander is enabled by default unless it is haptics sku */
1475 if (wsa884x->variant == WSA884X_OTP_ID_WSA8845H)
1476 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK,
1477 WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB);
1478 else
1479 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK,
1480 WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB);
1481 regmap_write(wsa884x->regmap, WSA884X_ANA_WO_CTL_0, wo_ctl_0);
1482
1483 wsa884x_set_gain_parameters(wsa884x);
1484
1485 wsa884x->hw_init = false;
1486 }
1487
wsa884x_update_status(struct sdw_slave * slave,enum sdw_slave_status status)1488 static int wsa884x_update_status(struct sdw_slave *slave,
1489 enum sdw_slave_status status)
1490 {
1491 struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev);
1492 int ret;
1493
1494 if (status == SDW_SLAVE_UNATTACHED) {
1495 wsa884x->hw_init = false;
1496 regcache_cache_only(wsa884x->regmap, true);
1497 regcache_mark_dirty(wsa884x->regmap);
1498 return 0;
1499 }
1500
1501 if (wsa884x->hw_init || status != SDW_SLAVE_ATTACHED)
1502 return 0;
1503
1504 regcache_cache_only(wsa884x->regmap, false);
1505 ret = regcache_sync(wsa884x->regmap);
1506 if (ret < 0) {
1507 dev_err(&slave->dev, "Cannot sync regmap cache\n");
1508 return ret;
1509 }
1510
1511 wsa884x_init(wsa884x);
1512
1513 return 0;
1514 }
1515
wsa884x_port_prep(struct sdw_slave * slave,struct sdw_prepare_ch * prepare_ch,enum sdw_port_prep_ops state)1516 static int wsa884x_port_prep(struct sdw_slave *slave,
1517 struct sdw_prepare_ch *prepare_ch,
1518 enum sdw_port_prep_ops state)
1519 {
1520 struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev);
1521
1522 if (state == SDW_OPS_PORT_POST_PREP)
1523 wsa884x->port_prepared[prepare_ch->num - 1] = true;
1524 else
1525 wsa884x->port_prepared[prepare_ch->num - 1] = false;
1526
1527 return 0;
1528 }
1529
1530 static const struct sdw_slave_ops wsa884x_slave_ops = {
1531 .update_status = wsa884x_update_status,
1532 .port_prep = wsa884x_port_prep,
1533 };
1534
wsa884x_dev_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1535 static int wsa884x_dev_mode_get(struct snd_kcontrol *kcontrol,
1536 struct snd_ctl_elem_value *ucontrol)
1537 {
1538 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1539 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
1540
1541 ucontrol->value.enumerated.item[0] = wsa884x->dev_mode;
1542
1543 return 0;
1544 }
1545
wsa884x_dev_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1546 static int wsa884x_dev_mode_put(struct snd_kcontrol *kcontrol,
1547 struct snd_ctl_elem_value *ucontrol)
1548 {
1549 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1550 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
1551
1552 if (wsa884x->dev_mode == ucontrol->value.enumerated.item[0])
1553 return 0;
1554
1555 wsa884x->dev_mode = ucontrol->value.enumerated.item[0];
1556
1557 return 1;
1558 }
1559
wsa884x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1560 static int wsa884x_get_swr_port(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_value *ucontrol)
1562 {
1563 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1564 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
1565 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1566 int portidx = mixer->reg;
1567
1568 ucontrol->value.integer.value[0] = wsa884x->port_enable[portidx];
1569
1570 return 0;
1571 }
1572
wsa884x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1573 static int wsa884x_set_swr_port(struct snd_kcontrol *kcontrol,
1574 struct snd_ctl_elem_value *ucontrol)
1575 {
1576 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1577 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
1578 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1579 int portidx = mixer->reg;
1580
1581 if (ucontrol->value.integer.value[0]) {
1582 if (wsa884x->port_enable[portidx])
1583 return 0;
1584
1585 wsa884x->port_enable[portidx] = true;
1586 } else {
1587 if (!wsa884x->port_enable[portidx])
1588 return 0;
1589
1590 wsa884x->port_enable[portidx] = false;
1591 }
1592
1593 return 1;
1594 }
1595
wsa884x_codec_probe(struct snd_soc_component * comp)1596 static int wsa884x_codec_probe(struct snd_soc_component *comp)
1597 {
1598 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
1599
1600 snd_soc_component_init_regmap(comp, wsa884x->regmap);
1601
1602 return 0;
1603 }
1604
wsa884x_spkr_post_pmu(struct snd_soc_component * component,struct wsa884x_priv * wsa884x)1605 static void wsa884x_spkr_post_pmu(struct snd_soc_component *component,
1606 struct wsa884x_priv *wsa884x)
1607 {
1608 unsigned int curr_limit, curr_ovrd_en;
1609
1610 wsa884x_set_gain_parameters(wsa884x);
1611 if (wsa884x->dev_mode == WSA884X_RECEIVER) {
1612 snd_soc_component_write_field(component, WSA884X_DRE_CTL_0,
1613 WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x3);
1614 snd_soc_component_write_field(component, WSA884X_CDC_PATH_MODE,
1615 WSA884X_CDC_PATH_MODE_RXD_MODE_MASK,
1616 0x1);
1617 snd_soc_component_write_field(component, WSA884X_PWM_CLK_CTL,
1618 WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK,
1619 0x1);
1620 } else {
1621 /* WSA884X_SPEAKER */
1622 snd_soc_component_write_field(component, WSA884X_DRE_CTL_0,
1623 WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0xf);
1624 }
1625
1626 if (wsa884x->port_enable[WSA884X_PORT_PBR]) {
1627 curr_ovrd_en = 0x0;
1628 curr_limit = 0x15;
1629 } else {
1630 curr_ovrd_en = 0x1;
1631 if (wsa884x->dev_mode == WSA884X_RECEIVER)
1632 curr_limit = 0x9;
1633 else
1634 curr_limit = 0x15;
1635 }
1636 snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT,
1637 WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK,
1638 curr_ovrd_en);
1639 snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT,
1640 WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK,
1641 curr_limit);
1642 }
1643
wsa884x_spkr_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1644 static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
1645 struct snd_kcontrol *kcontrol, int event)
1646 {
1647 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1648 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
1649
1650 switch (event) {
1651 case SND_SOC_DAPM_POST_PMU:
1652 wsa884x_spkr_post_pmu(component, wsa884x);
1653
1654 snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL,
1655 WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK,
1656 0x1);
1657 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
1658 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
1659 0x1);
1660
1661 break;
1662 case SND_SOC_DAPM_PRE_PMD:
1663 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
1664 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
1665 0x0);
1666 snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL,
1667 WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK,
1668 0x0);
1669 break;
1670 }
1671
1672 return 0;
1673 }
1674
1675 static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
1676 SND_SOC_DAPM_INPUT("IN"),
1677 SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
1678 };
1679
1680 static const DECLARE_TLV_DB_SCALE(pa_gain, -900, 150, -900);
1681
1682 static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
1683 SOC_SINGLE_RANGE_TLV("PA Volume", WSA884X_DRE_CTL_1,
1684 WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT,
1685 0x0, 0x1f, 1, pa_gain),
1686 SOC_ENUM_EXT("WSA MODE", wsa884x_dev_mode_enum,
1687 wsa884x_dev_mode_get, wsa884x_dev_mode_put),
1688 SOC_SINGLE_EXT("DAC Switch", WSA884X_PORT_DAC, 0, 1, 0,
1689 wsa884x_get_swr_port, wsa884x_set_swr_port),
1690 SOC_SINGLE_EXT("COMP Switch", WSA884X_PORT_COMP, 0, 1, 0,
1691 wsa884x_get_swr_port, wsa884x_set_swr_port),
1692 SOC_SINGLE_EXT("BOOST Switch", WSA884X_PORT_BOOST, 0, 1, 0,
1693 wsa884x_get_swr_port, wsa884x_set_swr_port),
1694 SOC_SINGLE_EXT("PBR Switch", WSA884X_PORT_PBR, 0, 1, 0,
1695 wsa884x_get_swr_port, wsa884x_set_swr_port),
1696 SOC_SINGLE_EXT("VISENSE Switch", WSA884X_PORT_VISENSE, 0, 1, 0,
1697 wsa884x_get_swr_port, wsa884x_set_swr_port),
1698 SOC_SINGLE_EXT("CPS Switch", WSA884X_PORT_CPS, 0, 1, 0,
1699 wsa884x_get_swr_port, wsa884x_set_swr_port),
1700 };
1701
1702 static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
1703 {"SPKR", NULL, "IN"},
1704 };
1705
1706 static const struct snd_soc_component_driver wsa884x_component_drv = {
1707 .name = "WSA884x",
1708 .probe = wsa884x_codec_probe,
1709 .controls = wsa884x_snd_controls,
1710 .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
1711 .dapm_widgets = wsa884x_dapm_widgets,
1712 .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
1713 .dapm_routes = wsa884x_audio_map,
1714 .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
1715 };
1716
wsa884x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1717 static int wsa884x_hw_params(struct snd_pcm_substream *substream,
1718 struct snd_pcm_hw_params *params,
1719 struct snd_soc_dai *dai)
1720 {
1721 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
1722 int i;
1723
1724 wsa884x->active_ports = 0;
1725 for (i = 0; i < WSA884X_MAX_SWR_PORTS; i++) {
1726 if (!wsa884x->port_enable[i])
1727 continue;
1728
1729 wsa884x->port_config[wsa884x->active_ports] = wsa884x_pconfig[i];
1730 wsa884x->active_ports++;
1731 }
1732
1733 wsa884x->sconfig.frame_rate = params_rate(params);
1734
1735 return sdw_stream_add_slave(wsa884x->slave, &wsa884x->sconfig,
1736 wsa884x->port_config, wsa884x->active_ports,
1737 wsa884x->sruntime);
1738 }
1739
wsa884x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1740 static int wsa884x_hw_free(struct snd_pcm_substream *substream,
1741 struct snd_soc_dai *dai)
1742 {
1743 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
1744
1745 sdw_stream_remove_slave(wsa884x->slave, wsa884x->sruntime);
1746
1747 return 0;
1748 }
1749
wsa884x_mute_stream(struct snd_soc_dai * dai,int mute,int stream)1750 static int wsa884x_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1751 {
1752 struct snd_soc_component *component = dai->component;
1753
1754 if (mute) {
1755 snd_soc_component_write_field(component, WSA884X_DRE_CTL_1,
1756 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1757 0x0);
1758 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
1759 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
1760 0x0);
1761
1762 } else {
1763 snd_soc_component_write_field(component, WSA884X_DRE_CTL_1,
1764 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1765 0x1);
1766 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
1767 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
1768 0x1);
1769 }
1770
1771 return 0;
1772 }
1773
wsa884x_set_stream(struct snd_soc_dai * dai,void * stream,int direction)1774 static int wsa884x_set_stream(struct snd_soc_dai *dai,
1775 void *stream, int direction)
1776 {
1777 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
1778
1779 wsa884x->sruntime = stream;
1780
1781 return 0;
1782 }
1783
1784 static const struct snd_soc_dai_ops wsa884x_dai_ops = {
1785 .hw_params = wsa884x_hw_params,
1786 .hw_free = wsa884x_hw_free,
1787 .mute_stream = wsa884x_mute_stream,
1788 .set_stream = wsa884x_set_stream,
1789 };
1790
1791 static struct snd_soc_dai_driver wsa884x_dais[] = {
1792 {
1793 .name = "SPKR",
1794 .playback = {
1795 .stream_name = "SPKR Playback",
1796 .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
1797 .formats = WSA884X_FORMATS,
1798 .rate_min = 8000,
1799 .rate_max = 384000,
1800 .channels_min = 1,
1801 .channels_max = 1,
1802 },
1803 .ops = &wsa884x_dai_ops,
1804 },
1805 };
1806
wsa884x_gpio_powerdown(void * data)1807 static void wsa884x_gpio_powerdown(void *data)
1808 {
1809 gpiod_direction_output(data, 1);
1810 }
1811
wsa884x_regulator_disable(void * data)1812 static void wsa884x_regulator_disable(void *data)
1813 {
1814 regulator_bulk_disable(WSA884X_SUPPLIES_NUM, data);
1815 }
1816
wsa884x_probe(struct sdw_slave * pdev,const struct sdw_device_id * id)1817 static int wsa884x_probe(struct sdw_slave *pdev,
1818 const struct sdw_device_id *id)
1819 {
1820 struct device *dev = &pdev->dev;
1821 struct wsa884x_priv *wsa884x;
1822 unsigned int i;
1823 int ret;
1824
1825 wsa884x = devm_kzalloc(dev, sizeof(*wsa884x), GFP_KERNEL);
1826 if (!wsa884x)
1827 return -ENOMEM;
1828
1829 for (i = 0; i < WSA884X_SUPPLIES_NUM; i++)
1830 wsa884x->supplies[i].supply = wsa884x_supply_name[i];
1831
1832 ret = devm_regulator_bulk_get(dev, WSA884X_SUPPLIES_NUM,
1833 wsa884x->supplies);
1834 if (ret)
1835 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1836
1837 ret = regulator_bulk_enable(WSA884X_SUPPLIES_NUM, wsa884x->supplies);
1838 if (ret)
1839 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1840
1841 ret = devm_add_action_or_reset(dev, wsa884x_regulator_disable,
1842 wsa884x->supplies);
1843 if (ret)
1844 return ret;
1845
1846 wsa884x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
1847 GPIOD_OUT_HIGH);
1848 if (IS_ERR(wsa884x->sd_n))
1849 return dev_err_probe(dev, PTR_ERR(wsa884x->sd_n),
1850 "Shutdown Control GPIO not found\n");
1851
1852 dev_set_drvdata(dev, wsa884x);
1853 wsa884x->slave = pdev;
1854 wsa884x->dev = dev;
1855 wsa884x->dev_mode = WSA884X_SPEAKER;
1856 wsa884x->sconfig.ch_count = 1;
1857 wsa884x->sconfig.bps = 1;
1858 wsa884x->sconfig.direction = SDW_DATA_DIR_RX;
1859 wsa884x->sconfig.type = SDW_STREAM_PDM;
1860
1861 pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS, 0);
1862 pdev->prop.simple_clk_stop_capable = true;
1863 pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop;
1864 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1865
1866 /* Bring out of reset */
1867 gpiod_direction_output(wsa884x->sd_n, 0);
1868 ret = devm_add_action_or_reset(dev, wsa884x_gpio_powerdown, wsa884x->sd_n);
1869 if (ret)
1870 return ret;
1871
1872 wsa884x->regmap = devm_regmap_init_sdw(pdev, &wsa884x_regmap_config);
1873 if (IS_ERR(wsa884x->regmap))
1874 return dev_err_probe(dev, PTR_ERR(wsa884x->regmap),
1875 "regmap_init failed\n");
1876
1877 /* Start in cache-only until device is enumerated */
1878 regcache_cache_only(wsa884x->regmap, true);
1879 wsa884x->hw_init = true;
1880
1881 pm_runtime_set_autosuspend_delay(dev, 3000);
1882 pm_runtime_use_autosuspend(dev);
1883 pm_runtime_mark_last_busy(dev);
1884 pm_runtime_set_active(dev);
1885 pm_runtime_enable(dev);
1886
1887 return devm_snd_soc_register_component(dev,
1888 &wsa884x_component_drv,
1889 wsa884x_dais,
1890 ARRAY_SIZE(wsa884x_dais));
1891 }
1892
wsa884x_runtime_suspend(struct device * dev)1893 static int __maybe_unused wsa884x_runtime_suspend(struct device *dev)
1894 {
1895 struct regmap *regmap = dev_get_regmap(dev, NULL);
1896
1897 regcache_cache_only(regmap, true);
1898 regcache_mark_dirty(regmap);
1899
1900 return 0;
1901 }
1902
wsa884x_runtime_resume(struct device * dev)1903 static int __maybe_unused wsa884x_runtime_resume(struct device *dev)
1904 {
1905 struct regmap *regmap = dev_get_regmap(dev, NULL);
1906
1907 regcache_cache_only(regmap, false);
1908 regcache_sync(regmap);
1909
1910 return 0;
1911 }
1912
1913 static const struct dev_pm_ops wsa884x_pm_ops = {
1914 SET_RUNTIME_PM_OPS(wsa884x_runtime_suspend, wsa884x_runtime_resume, NULL)
1915 };
1916
1917 static const struct sdw_device_id wsa884x_swr_id[] = {
1918 SDW_SLAVE_ENTRY(0x0217, 0x204, 0),
1919 {},
1920 };
1921 MODULE_DEVICE_TABLE(sdw, wsa884x_swr_id);
1922
1923 static struct sdw_driver wsa884x_codec_driver = {
1924 .driver = {
1925 .name = "wsa884x-codec",
1926 .pm = &wsa884x_pm_ops,
1927 },
1928 .probe = wsa884x_probe,
1929 .ops = &wsa884x_slave_ops,
1930 .id_table = wsa884x_swr_id,
1931 };
1932 module_sdw_driver(wsa884x_codec_driver);
1933
1934 MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>");
1935 MODULE_DESCRIPTION("WSA884x codec driver");
1936 MODULE_LICENSE("GPL");
1937
