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Searched refs:GENMO_WT__VGA_VSYNC_POL__SHIFT (Results 1 – 18 of 18) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h7180 #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007 macro
Ddce_8_0_sh_mask.h10618 #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 macro
Ddce_10_0_sh_mask.h11002 #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 macro
Ddce_11_0_sh_mask.h10814 #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 macro
Ddce_11_2_sh_mask.h12068 #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 macro
Ddce_12_0_sh_mask.h2208 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h245 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_0_1_sh_mask.h340 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_2_1_sh_mask.h4443 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_1_0_sh_mask.h847 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_1_5_sh_mask.h5148 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_1_2_sh_mask.h340 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_0_2_sh_mask.h258 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_1_4_sh_mask.h7795 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_1_6_sh_mask.h355 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_0_0_sh_mask.h239 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_2_0_0_sh_mask.h258 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro
Ddcn_3_2_0_sh_mask.h4442 #define GENMO_WT__VGA_VSYNC_POL__SHIFT … macro