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Searched refs:GENMO_WT__VGA_HSYNC_POL__SHIFT (Results 1 – 18 of 18) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h7176 #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006 macro
Ddce_8_0_sh_mask.h10616 #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 macro
Ddce_10_0_sh_mask.h11000 #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 macro
Ddce_11_0_sh_mask.h10812 #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 macro
Ddce_11_2_sh_mask.h12066 #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 macro
Ddce_12_0_sh_mask.h2207 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h244 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_0_1_sh_mask.h339 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_2_1_sh_mask.h4442 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_1_0_sh_mask.h846 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_1_5_sh_mask.h5147 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_1_2_sh_mask.h339 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_0_2_sh_mask.h257 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_1_4_sh_mask.h7794 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_1_6_sh_mask.h354 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_0_0_sh_mask.h238 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_2_0_0_sh_mask.h257 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro
Ddcn_3_2_0_sh_mask.h4441 #define GENMO_WT__VGA_HSYNC_POL__SHIFT macro