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Searched refs:GC_HWIP (Results 1 – 25 of 49) sorted by relevance

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/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dsoc15_common.h111 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0)
118 …uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG…
119 …uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
120 …uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC…
139 …_((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)
143 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
155 …uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
156 …uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
157 …uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRB…
158 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRB…
[all …]
Dgmc_v9_0.c642 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) in gmc_v9_0_process_interrupt()
656 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
773 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gmc_v9_0_use_invalidate_semaphore()
774 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) in gmc_v9_0_use_invalidate_semaphore()
825 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { in gmc_v9_0_flush_gpu_tlb()
835 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && in gmc_v9_0_flush_gpu_tlb()
897 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
970 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); in gmc_v9_0_flush_gpu_tlb_pasid()
985 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && in gmc_v9_0_flush_gpu_tlb_pasid()
1193 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v9_0_get_coherence_flags()
[all …]
Damdgpu_discovery.c180 [GC_HWIP] = GC_HWID,
308 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { in amdgpu_discovery_harvest_config_quirk()
1359 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0) && in amdgpu_discovery_harvest_ip()
1360 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) { in amdgpu_discovery_harvest_ip()
1603 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_common_ip_blocks()
1640 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_common_ip_blocks()
1649 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gmc_ip_blocks()
1686 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gmc_ip_blocks()
1908 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gc_ip_blocks()
1949 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gc_ip_blocks()
[all …]
Dgmc_v10_0.c148 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
246 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
281 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
714 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
828 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_mc_init()
895 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
913 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
1217 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) || in gmc_v10_0_get_clockgating_state()
1218 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) in gmc_v10_0_get_clockgating_state()
Dgfx_v9_0.c898 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_golden_registers()
954 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_init_golden_registers()
955 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) in gfx_v9_0_init_golden_registers()
1098 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_check_fw_write_wait()
1105 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_fw_write_wait()
1205 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && in check_if_enlarge_doorbell_range()
1218 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_if_need_gfxoff()
1329 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gfx_v9_0_load_mec2_fw_bin_support()
1330 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || in gfx_v9_0_load_mec2_fw_bin_support()
1331 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) in gfx_v9_0_load_mec2_fw_bin_support()
[all …]
Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
Dmes_v10_1.c304 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; in mes_v10_1_set_hw_resources()
561 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
571 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
581 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
590 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_load_microcode()
998 switch (adev->ip_versions[GC_HWIP][0]) { in mes_v10_1_kiq_setting()
Dgfx_v10_0.c3630 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_spm_golden_registers()
3653 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_golden_registers()
3894 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_fw_write_wait()
3945 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_check_gfxoff_flag()
3967 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && in gfx_v10_0_init_microcode()
3970 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in gfx_v10_0_init_microcode()
4147 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_init_rlcg_reg_access_ctrl()
4361 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_gpu_early_init()
4494 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v10_0_sw_init()
4752 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || in gfx_v10_0_setup_rb()
[all …]
Damdgpu_display.c769 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
771 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) in convert_tiling_flags_to_modifier()
773 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) in convert_tiling_flags_to_modifier()
782 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
788 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
844 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); in convert_tiling_flags_to_modifier()
881 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && in convert_tiling_flags_to_modifier()
Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
Dpsp_v10_0.c61 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 1, 0)) && in psp_v10_0_init_microcode()
Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
Dimu_v11_0.c50 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v11_0_init_microcode()
355 switch (adev->ip_versions[GC_HWIP][0]) { in imu_v11_0_program_rlc_ram()
Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
Dgmc_v11_0.c207 GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_vm_hub()
628 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_set_gfxhub_funcs()
778 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v11_0_sw_init()
Damdgpu_ucode.c1210 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) in amdgpu_ucode_legacy_naming()
1222 } else if (block_type == GC_HWIP) { in amdgpu_ucode_legacy_naming()
1223 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1285 case GC_HWIP: in amdgpu_ucode_ip_version_decode()
Daqua_vanjaram.c216 case GC_HWIP: in aqua_vanjaram_logical_to_dev_inst()
267 { GC_HWIP, adev->gfx.xcc_mask }, in aqua_vanjaram_ip_map_init()
Damdgpu_gmc.c587 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_gmc_tmz_set()
651 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; in amdgpu_gmc_noretry_set()
Damdgpu_mes.c1338 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0) && in amdgpu_mes_self_test()
1339 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0) && in amdgpu_mes_self_test()
1398 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, in amdgpu_mes_init_microcode()
1400 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) { in amdgpu_mes_init_microcode()
Dsoc15.c461 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
474 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
938 switch (adev->ip_versions[GC_HWIP][0]) { in soc15_common_early_init()
Dsoc21.c450 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_need_full_reset()
578 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_common_early_init()
Dgfxhub_v1_2.c362 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gfxhub_v1_2_xcc_setup_vmid_config()
363 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)); in gfxhub_v1_2_xcc_setup_vmid_config()
Damdgpu_device.c892 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) || in amdgpu_device_asic_init()
893 adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) { in amdgpu_device_asic_init()
2734 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)) in amdgpu_device_smu_fini_early()
3479 else if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) && in amdgpu_device_set_mcbp()
3480 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) && in amdgpu_device_set_mcbp()
3696 (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))) { in amdgpu_device_init()
5324 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in amdgpu_device_gpu_recover()
5325 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) in amdgpu_device_gpu_recover()
5350 if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)) in amdgpu_device_gpu_recover()
/Linux-v6.6/drivers/gpu/drm/amd/amdkfd/
Dkfd_device.c282 switch (adev->ip_versions[GC_HWIP][0]) { in kgd2kfd_probe()
423 if (adev->ip_versions[GC_HWIP][0]) in kgd2kfd_probe()
425 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); in kgd2kfd_probe()

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