Searched refs:GCR (Results 1 – 11 of 11) sorted by relevance
127 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa25x()132 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa25x()133 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa25x()137 writel(GCR_COLD_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa25x()149 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa27x()156 …writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything bu… in pxa_ac97_cold_pxa27x()157 writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */ in pxa_ac97_cold_pxa27x()165 writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR); in pxa_ac97_cold_pxa27x()175 writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR); in pxa_ac97_warm_pxa3xx()181 writel(0, ac97_reg_base + GCR); in pxa_ac97_cold_pxa3xx()[all …]
21 #define GCR (0x000C) /* Global Control Register */ macro
37 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
123 #define GCR 0x00 /* (SIR0) General Configuration Register */ macro1378 atmel_write16(dev, GCR, 0x0060); in atmel_close()1379 atmel_write16(dev, GCR, 0x0040); in atmel_close()1630 atmel_write16(dev, GCR, 0x0060); in stop_atmel_card()1631 atmel_write16(dev, GCR, 0x0040); in stop_atmel_card()3672 atmel_write16(dev, GCR, 0x0060); in probe_atmel_card()3674 atmel_write16(dev, GCR, 0x0040); in probe_atmel_card()3699 atmel_write16(dev, GCR, 0x0060); in probe_atmel_card()3700 atmel_write16(dev, GCR, 0x0040); in probe_atmel_card()3722 atmel_write16(dev, GCR, 0x0060); in probe_atmel_card()[all …]
1115 reg_data = er32(GCR); in e1000_init_hw_82571()1117 ew32(GCR, reg_data); in e1000_init_hw_82571()1247 reg = er32(GCR); in e1000_initialize_hw_bits_82571()1249 ew32(GCR, reg); in e1000_initialize_hw_bits_82571()
1679 gcr = er32(GCR); in e1000e_set_pcie_no_snoop()1682 ew32(GCR, gcr); in e1000e_set_pcie_no_snoop()
140 GCR, GSCR, GRST1, HW_ID, enumerator
36 [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
3082 u8 GCR; in velocity_set_wol() local3083 GCR = readb(®s->CHIPGCR); in velocity_set_wol()3084 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX; in velocity_set_wol()3085 writeb(GCR, ®s->CHIPGCR); in velocity_set_wol()
1581 od->context.gcr = omap_dma_glbl_read(od, GCR); in omap_dma_context_save()1588 omap_dma_glbl_write(od, GCR, od->context.gcr); in omap_dma_context_restore()1644 omap_dma_glbl_write(od, GCR, val); in omap_dma_init_gcr()
41 #define GCR 0x004C /* Global control register */ macro
