Searched refs:EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ (Results 1 – 1 of 1) sorted by relevance
64 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0) macro153 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ; in exynos4x12_rate_to_clk()