Searched refs:DUMP_REG (Results 1 – 10 of 10) sorted by relevance
234 #define DUMP_REG(addr) do { \ in kgd_hqd_dump() macro247 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); in kgd_hqd_dump()248 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); in kgd_hqd_dump()249 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); in kgd_hqd_dump()250 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); in kgd_hqd_dump()253 DUMP_REG(reg); in kgd_hqd_dump()332 DUMP_REG(sdma_offset + reg); in kgd_hqd_sdma_dump()335 DUMP_REG(sdma_offset + reg); in kgd_hqd_sdma_dump()338 DUMP_REG(sdma_offset + reg); in kgd_hqd_sdma_dump()341 DUMP_REG(sdma_offset + reg); in kgd_hqd_sdma_dump()[all …]
210 #define DUMP_REG(addr) do { \ in kgd_hqd_dump() macro223 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); in kgd_hqd_dump()224 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); in kgd_hqd_dump()225 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); in kgd_hqd_dump()226 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); in kgd_hqd_dump()229 DUMP_REG(reg); in kgd_hqd_dump()309 DUMP_REG(sdma_offset + reg); in kgd_hqd_sdma_dump()312 DUMP_REG(sdma_offset + reg); in kgd_hqd_sdma_dump()
56 #define DUMP_REG(addr) do { \ macro208 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()210 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()213 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()216 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_arcturus_hqd_sdma_dump()
334 #define DUMP_REG(addr) do { \ in hqd_dump_v10_3() macro349 DUMP_REG(reg); in hqd_dump_v10_3()443 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()445 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()448 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()451 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v10_3()
137 #define DUMP_REG(addr) do { \ in kgd_gfx_v9_4_3_hqd_sdma_dump() macro149 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()151 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()154 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()157 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_gfx_v9_4_3_hqd_sdma_dump()
319 #define DUMP_REG(addr) do { \ in hqd_dump_v11() macro334 DUMP_REG(reg); in hqd_dump_v11()429 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()432 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()435 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()438 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()441 DUMP_REG(sdma_rlc_reg_offset + reg); in hqd_sdma_dump_v11()
348 #define DUMP_REG(addr) do { \ in kgd_hqd_dump() macro363 DUMP_REG(reg); in kgd_hqd_dump()457 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()459 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()462 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()465 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
361 #define DUMP_REG(addr) do { \ in kgd_gfx_v9_hqd_dump() macro376 DUMP_REG(reg); in kgd_gfx_v9_hqd_dump()470 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()472 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()475 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()478 DUMP_REG(sdma_rlc_reg_offset + reg); in kgd_hqd_sdma_dump()
27 #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ } macro34 #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)37 #define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)
240 #undef DUMP_REG254 #ifdef DUMP_REG in nvidia_write_regs()269 #ifdef DUMP_REG in nvidia_write_regs()277 #ifdef DUMP_REG in nvidia_write_regs()284 #ifdef DUMP_REG in nvidia_write_regs()
