Searched refs:DSP (Results 1 – 25 of 89) sorted by relevance
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33 in1_input Measured voltage for 1V8 DSP (milliVolts)34 in1_label "1V8 DSP"35 curr2_input Measured current for 1V8 DSP (milliAmps)36 curr2_label "1V8 DSP"37 power2_average Measured average power for 1V8 DSP (microWatts)39 power2_label "1V8 DSP"47 in3_input Measured voltage for VDDCORE DSP (milliVolts)48 in3_label "VDDCORE DSP"49 curr4_input Measured current for VDDCORE DSP (milliAmps)50 curr4_label "VDDCORE DSP"[all …]
1 Keystone 2 DSP GPIO controller bindings3 HOST OS userland running on ARM can send interrupts to DSP cores using4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.7 For example TCI6638K2K SoC has 8 DSP GPIO controllers:10 Keystone 2 DSP GPIO controller has specific features:12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
1 TI Davinci DSP devices7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that13 controller, a dedicated local power/sleep controller etc. The DSP processor14 core used in Davinci SoCs is usually a C674x DSP CPU.16 DSP Device Node:18 Each DSP Core sub-system is represented as a single DT node.38 interrupts from the DSP. The value should follow the52 /* DSP Reserved Memory node */65 /* DSP node */
1 TI Keystone DSP devices4 The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core10 a dedicated local power/sleep controller etc. The DSP processor core in13 DSP Device Node:15 Each DSP Core sub-system is represented as a single DT node, and should also42 State Control node, and the register offset of the DSP83 and an args specifier containing the DSP device id101 /* 66AK2H/K DSP aliases */113 /* 66AK2H/K DSP memory node */126 /* 66AK2H/K DSP node */[all …]
10 digital audio to I2S DAI0, I2S DAI1 or PDM DAI2. This is useful for on SoC DSP15 graph representing the DSP internal audio paths and uses the mixer settings to22 Phone Audio System with SoC based DSP29 | Front End PCMs | SoC DSP | Back End DAIs | Audio devices |35 * DSP *47 modem. This sound card exposes 4 DSP front end (FE) ALSA PCM devices and66 * DSP *83 * DSP *130 | Front End PCMs | SoC DSP | Back End DAIs | Audio devices |136 * DSP *[all …]
6 drivers and DSP drivers. The platform drivers only target the SoC CPU and must68 SoC DSP Drivers71 Each SoC DSP driver usually supplies the following features :-75 3. DMA IO to/from DSP buffers (if applicable)76 4. Definition of DSP front end (FE) PCM devices.
64 .name = "CPU-DSP",65 .stream_name = "CPU-DSP",76 .name = "DSP-CODEC",77 .stream_name = "DSP-CODEC",
109 Inter widget audio data buffer within a DSP.111 DSP internal scheduler that schedules component/pipeline processing116 Sample Rate Converter within DSP or CODEC118 Asynchronous Sample Rate Converter within DSP or CODEC200 machine audio component (non codec or DSP) that can be independently245 Codec/DSP Widget Interconnections252 This is easiest with a diagram of the codec or DSP (and schematic of the machine
3 tristate "IMX DSP Protocol driver"6 This enables DSP IPC protocol between host AP (Linux)7 and the firmware running on DSP.8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).11 exchange information with DSP side.
2 E-MU Digital Audio System mixer / default DSP code65 and the DSP microcontroller can operate with the resulting sum.102 samples for 5.1 playback. The result samples are forwarded to the DSP 0 & 1109 samples for 5.1 playback. The result samples are forwarded to the DSP 2 & 3116 samples for 7.1 playback. The result samples are forwarded to the DSP 6 & 7123 are forwarded to the DSP 4 playback channel.129 are forwarded to the DSP 5 playback channel.158 The result samples are forwarded to the DSP 0 & 1 playback channels.163 The result samples are forwarded to the DSP 2 & 3 playback channels.168 The result samples are forwarded to the DSP 6 & 7 playback channels.[all …]
40 prompt "DSP support"44 have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).46 This option must be set in order to enable the DSP.
9 has an audio controller with a DSP and I2S or DMIC port, then93 If you have a Intel Skylake platform with the DSP enabled102 If you have a Intel Broxton/ApolloLake platform with the DSP111 If you have a Intel Kabylake platform with the DSP120 If you have a Intel GeminiLake platform with the DSP129 If you have a Intel CNL/WHL platform with the DSP138 If you have a Intel CoffeeLake platform with the DSP147 If you have a Intel CometLake-H platform with the DSP156 If you have a Intel CometLake-LP platform with the DSP185 GeminiLake or CannonLake platform with the DSP enabled in the BIOS[all …]
54 DSP, /* CXL Downstream Switch Port */ enumerator79 case DSP: in cper_print_prot_err()105 case DSP: in cper_print_prot_err()146 case DSP: in cper_print_prot_err()
17 In recent years, audio digital signal processors (DSP) were integrated68 streaming compressed data to a DSP, with the assumption that the75 DSP, eg. Android HAL or PulseAudio sinks. By construction, regular95 is transmitted to the audio DSP. DMA transfers from main memory to an132 This routines returns the actual settings used by the DSP. Changes to140 refilled or the delay due to decoding/encoding/io on the DSP.216 So we need to pass this to DSP. This metadata is extracted from ID3/MP4 headers218 interface to pass this information to the DSP. Also DSP and userspace needs to229 This routine tells DSP that metadata and write operation sent after this would233 This is called when end of file is reached. The userspace can inform DSP that[all …]
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances27 is required for DSP IOMMU instances on DRA7xx SoCs. The28 instance number should be 0 for DSP MDMA MMUs and 1 for29 DSP EDMA MMUs.
12 Support for remote processors (such as DSP coprocessors). These38 tristate "i.MX DSP remoteproc support"43 Say y here to support iMX's DSP remote processors via the remote75 and DSP on OMAP4) via the remote processor framework.81 offloaded to remote DSP processors using this framework).120 offloaded to remote DSP processors using this framework).123 loaded on the DSP. This file must reside in the /lib/firmware135 Say Y here here to support Keystone remote processors (DSP)233 used to control subsystems such as ADSP (Audio DSP),234 CDSP (Compute DSP), MPSS (Modem Peripheral SubSystem), and[all …]
371 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"385 prompt "DSP support"388 Depending on the configuration, CPU can contain DSP registers394 bool "No DSP extension presence in HW"396 No DSP extension presence in HW399 bool "DSP extension in HW, no support for userspace"403 DSP extension presence in HW, no support for DSP-enabled userspace404 applications. We don't save / restore DSP registers and only do408 bool "Support DSP for userspace apps"413 DSP extension presence in HW, support save / restore DSP registers to[all …]
1 * TI - DSP (Digital Signal Processor)3 TI DSP included in OMAP SoC
45 1.c) The Digital Signal Processor (DSP) node53 - reg : should contain the DSP registers location and length54 - interrupts : should contain the DSP interrupt60 The ARAM node must be placed under the DSP node.
56 1.c) The Digital Signal Processor (DSP) node64 - reg : should contain the DSP registers location and length65 - interrupts : should contain the DSP interrupt
6 generic open source audio DSP firmware for multiple devices.177 if you are trying to debug IPC with the DSP firmware.196 memory -> DSP resource (memory, register, etc)197 before the audio DSP is suspended. This will increase the suspend216 which can be used to flood the DSP with test IPCs and gather stats235 crafted IPC messages to the DSP to test its robustness.246 DSP messages.251 bool "SOF retain DSP context on any FW exceptions"253 This option keeps the DSP in D0 state so that firmware debug255 Say Y if you want to retain DSP context for FW exceptions.
3 On Keystone SOCs, DSP cores can send interrupts to ARM5 The IRQ handler running on HOST OS can identify DSP signal source by
26 tristate "SOF support for MT8186 audio DSP"36 tristate "SOF support for MT8195 audio DSP"
3 * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms
94 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN185 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN255 - hand-over to the DSP for access to multi-link registers, SHIM/IP
