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Searched refs:DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h22984 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_0_1_sh_mask.h38341 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_2_1_0_sh_mask.h45105 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_2_1_sh_mask.h42534 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_1_5_sh_mask.h45579 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_1_2_sh_mask.h47298 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_0_2_sh_mask.h44368 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_1_4_sh_mask.h49637 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_1_6_sh_mask.h48925 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_0_0_sh_mask.h51001 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_2_0_0_sh_mask.h51672 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro
Ddcn_3_2_0_sh_mask.h42486 #define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT … macro