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Searched refs:DPU_REG_WRITE (Results 1 – 15 of 15) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_util.c173 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3_lut()
183 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); in _dpu_hw_setup_scaler3_lut()
197 DPU_REG_WRITE(c, QSEED3LITE_DIR_FILTER_WEIGHT + offset, scaler3_cfg->dir_weight); in _dpu_hw_setup_scaler3lite_lut()
225 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3lite_lut()
234 DPU_REG_WRITE(c, QSEED3_COEF_LUT_CTRL + offset, BIT(0)); in _dpu_hw_setup_scaler3lite_lut()
272 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN + offset, sharp_lvl); in _dpu_hw_setup_scaler3_de()
273 DPU_REG_WRITE(c, QSEED3_DE_SHARPEN_CTL + offset, sharp_ctl); in _dpu_hw_setup_scaler3_de()
274 DPU_REG_WRITE(c, QSEED3_DE_SHAPE_CTL + offset, shape_ctl); in _dpu_hw_setup_scaler3_de()
275 DPU_REG_WRITE(c, QSEED3_DE_THRESHOLD + offset, de_thr); in _dpu_hw_setup_scaler3_de()
276 DPU_REG_WRITE(c, QSEED3_DE_ADJUST_DATA_0 + offset, adjust_a); in _dpu_hw_setup_scaler3_de()
[all …]
Ddpu_hw_dsc_1_2.c79 DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, 0); in dpu_hw_dsc_disable_1_2()
81 DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, 0); in dpu_hw_dsc_disable_1_2()
82 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, 0); in dpu_hw_dsc_disable_1_2()
116 DPU_REG_WRITE(hw, DSC_CMN_MAIN_CNF, data); in dpu_hw_dsc_config_1_2()
125 DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, data); in dpu_hw_dsc_config_1_2()
153 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, data); in dpu_hw_dsc_config_1_2()
158 DPU_REG_WRITE(hw, sblk->enc.base + DSC_PICTURE_SIZE, data); in dpu_hw_dsc_config_1_2()
163 DPU_REG_WRITE(hw, sblk->enc.base + DSC_SLICE_SIZE, data); in dpu_hw_dsc_config_1_2()
165 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MISC_SIZE, in dpu_hw_dsc_config_1_2()
171 DPU_REG_WRITE(hw, sblk->enc.base + DSC_HRD_DELAYS, data); in dpu_hw_dsc_config_1_2()
[all …]
Ddpu_hw_dsc.c40 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); in dpu_hw_dsc_disable()
54 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); in dpu_hw_dsc_config()
71 DPU_REG_WRITE(c, DSC_ENC, data); in dpu_hw_dsc_config()
75 DPU_REG_WRITE(c, DSC_PICTURE, data); in dpu_hw_dsc_config()
79 DPU_REG_WRITE(c, DSC_SLICE, data); in dpu_hw_dsc_config()
82 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); in dpu_hw_dsc_config()
86 DPU_REG_WRITE(c, DSC_DELAY, data); in dpu_hw_dsc_config()
89 DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data); in dpu_hw_dsc_config()
92 DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data); in dpu_hw_dsc_config()
95 DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data); in dpu_hw_dsc_config()
[all …]
Ddpu_hw_intf.c212 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); in dpu_hw_intf_setup_timing_engine()
213 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); in dpu_hw_intf_setup_timing_engine()
214 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, in dpu_hw_intf_setup_timing_engine()
216 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl); in dpu_hw_intf_setup_timing_engine()
217 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start); in dpu_hw_intf_setup_timing_engine()
218 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); in dpu_hw_intf_setup_timing_engine()
219 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl); in dpu_hw_intf_setup_timing_engine()
220 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start); in dpu_hw_intf_setup_timing_engine()
221 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end); in dpu_hw_intf_setup_timing_engine()
222 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr); in dpu_hw_intf_setup_timing_engine()
[all …]
Ddpu_hw_wb.c57 DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]); in dpu_hw_wb_setup_outaddress()
58 DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]); in dpu_hw_wb_setup_outaddress()
59 DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]); in dpu_hw_wb_setup_outaddress()
60 DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]); in dpu_hw_wb_setup_outaddress()
109 DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF); in dpu_hw_wb_setup_format()
110 DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format); in dpu_hw_wb_setup_format()
111 DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode); in dpu_hw_wb_setup_format()
112 DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern); in dpu_hw_wb_setup_format()
113 DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0); in dpu_hw_wb_setup_format()
114 DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1); in dpu_hw_wb_setup_format()
[all …]
Ddpu_hw_dspp.c45 DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); in dpu_setup_dspp_pcc()
49 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r); in dpu_setup_dspp_pcc()
50 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g); in dpu_setup_dspp_pcc()
51 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b); in dpu_setup_dspp_pcc()
53 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r); in dpu_setup_dspp_pcc()
54 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g); in dpu_setup_dspp_pcc()
55 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b); in dpu_setup_dspp_pcc()
57 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r); in dpu_setup_dspp_pcc()
58 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g); in dpu_setup_dspp_pcc()
59 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b); in dpu_setup_dspp_pcc()
[all …]
Ddpu_hw_sspp.c165 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask); in dpu_hw_sspp_setup_multirect()
185 DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); in _sspp_setup_opmode()
200 DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode); in _sspp_setup_csc10_opmode()
272 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, in dpu_hw_sspp_setup_format()
278 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
285 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
290 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
295 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
319 DPU_REG_WRITE(c, format_off, src_format); in dpu_hw_sspp_setup_format()
320 DPU_REG_WRITE(c, unpack_pat_off, unpack); in dpu_hw_sspp_setup_format()
[all …]
Ddpu_hw_pingpong.c54 DPU_REG_WRITE(c, base + PP_DITHER_EN, 0); in dpu_hw_pp_setup_dither()
64 DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data); in dpu_hw_pp_setup_dither()
71 DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data); in dpu_hw_pp_setup_dither()
73 DPU_REG_WRITE(c, base + PP_DITHER_EN, 1); in dpu_hw_pp_setup_dither()
92 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_enable_te()
93 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); in dpu_hw_pp_enable_te()
94 DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val); in dpu_hw_pp_enable_te()
95 DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq); in dpu_hw_pp_enable_te()
96 DPU_REG_WRITE(c, PP_START_POS, te->start_pos); in dpu_hw_pp_enable_te()
97 DPU_REG_WRITE(c, PP_SYNC_THRESH, in dpu_hw_pp_enable_te()
[all …]
Ddpu_hw_ctl.c83 DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); in dpu_hw_ctl_trigger_start()
95 DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1); in dpu_hw_ctl_trigger_pending()
130 DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
133 DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
136 DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
142 DPU_REG_WRITE(&ctx->hw, in dpu_hw_ctl_trigger_flush_v1()
148 DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
151 DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); in dpu_hw_ctl_trigger_flush_v1()
158 DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); in dpu_hw_ctl_trigger_flush()
375 DPU_REG_WRITE(c, CTL_SW_RESET, 0x1); in dpu_hw_ctl_reset_control()
[all …]
Ddpu_hw_lm.c58 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); in dpu_hw_lm_setup_out()
65 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_out()
75 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, in dpu_hw_lm_setup_border_color()
78 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, in dpu_hw_lm_setup_border_color()
109 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); in dpu_hw_lm_setup_blend_config_combined_alpha()
110 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config_combined_alpha()
126 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); in dpu_hw_lm_setup_blend_config()
127 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); in dpu_hw_lm_setup_blend_config()
128 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config()
142 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_color3()
Ddpu_hw_top.c60 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); in dpu_hw_setup_split_pipe()
61 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); in dpu_hw_setup_split_pipe()
62 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); in dpu_hw_setup_split_pipe()
63 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); in dpu_hw_setup_split_pipe()
92 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
171 DPU_REG_WRITE(c, wd_load_value, in dpu_hw_setup_vsync_source()
174 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ in dpu_hw_setup_vsync_source()
178 DPU_REG_WRITE(c, wd_ctl2, reg); in dpu_hw_setup_vsync_source()
207 DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); in dpu_hw_setup_vsync_source_and_vsync_sel()
250 DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); in dpu_hw_intf_audio_select()
Ddpu_hw_vbif.c52 DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src); in dpu_hw_clear_errors()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
141 DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); in dpu_hw_set_halt_ctrl()
181 DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); in dpu_hw_set_qos_remap()
182 DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl); in dpu_hw_set_qos_remap()
197 DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); in dpu_hw_set_write_gather_en()
Ddpu_hw_merge3d.c26 DPU_REG_WRITE(c, MERGE_3D_MODE, 0); in dpu_hw_merge_3d_setup_3d_mode()
27 DPU_REG_WRITE(c, MERGE_3D_MUX, 0); in dpu_hw_merge_3d_setup_3d_mode()
30 DPU_REG_WRITE(c, MERGE_3D_MODE, data); in dpu_hw_merge_3d_setup_3d_mode()
Ddpu_hw_interrupts.c250 DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, in dpu_core_irq()
321 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_enable_irq_locked()
323 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_enable_irq_locked()
370 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_disable_irq_locked()
372 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_disable_irq_locked()
396 DPU_REG_WRITE(&intr->hw, in dpu_clear_irqs()
414 DPU_REG_WRITE(&intr->hw, in dpu_disable_all_irqs()
450 DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, in dpu_core_irq_read()
Ddpu_hw_util.h333 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) macro