1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef DC_TYPES_H_
26 #define DC_TYPES_H_
27 
28 /* AND EdidUtility only needs a portion
29  * of this file, including the rest only
30  * causes additional issues.
31  */
32 #include "os_types.h"
33 #include "fixed31_32.h"
34 #include "irq_types.h"
35 #include "dc_ddc_types.h"
36 #include "dc_dp_types.h"
37 #include "dc_hdmi_types.h"
38 #include "dc_hw_types.h"
39 #include "dal_types.h"
40 #include "grph_object_defs.h"
41 #include "grph_object_ctrl_defs.h"
42 
43 #include "dm_cp_psp.h"
44 
45 /* forward declarations */
46 struct dc_plane_state;
47 struct dc_stream_state;
48 struct dc_link;
49 struct dc_sink;
50 struct dal;
51 struct dc_dmub_srv;
52 
53 /********************************
54  * Environment definitions
55  ********************************/
56 enum dce_environment {
57 	DCE_ENV_PRODUCTION_DRV = 0,
58 	/* Emulation on FPGA, in "Maximus" System.
59 	 * This environment enforces that *only* DC registers accessed.
60 	 * (access to non-DC registers will hang FPGA) */
61 	DCE_ENV_FPGA_MAXIMUS,
62 	/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
63 	 * requirements of Diagnostics team. */
64 	DCE_ENV_DIAG,
65 	/*
66 	 * Guest VM system, DC HW may exist but is not virtualized and
67 	 * should not be used.  SW support for VDI only.
68 	 */
69 	DCE_ENV_VIRTUAL_HW
70 };
71 
72 struct dc_perf_trace {
73 	unsigned long read_count;
74 	unsigned long write_count;
75 	unsigned long last_entry_read;
76 	unsigned long last_entry_write;
77 };
78 
79 #define MAX_SURFACE_NUM 6
80 #define NUM_PIXEL_FORMATS 10
81 
82 enum tiling_mode {
83 	TILING_MODE_INVALID,
84 	TILING_MODE_LINEAR,
85 	TILING_MODE_TILED,
86 	TILING_MODE_COUNT
87 };
88 
89 enum view_3d_format {
90 	VIEW_3D_FORMAT_NONE = 0,
91 	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
92 	VIEW_3D_FORMAT_SIDE_BY_SIDE,
93 	VIEW_3D_FORMAT_TOP_AND_BOTTOM,
94 	VIEW_3D_FORMAT_COUNT,
95 	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
96 };
97 
98 enum plane_stereo_format {
99 	PLANE_STEREO_FORMAT_NONE = 0,
100 	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
101 	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
102 	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
103 	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
104 	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
105 	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
106 };
107 
108 /* TODO: Find way to calculate number of bits
109  *  Please increase if pixel_format enum increases
110  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
111  */
112 
113 enum dc_edid_connector_type {
114 	DC_EDID_CONNECTOR_UNKNOWN = 0,
115 	DC_EDID_CONNECTOR_ANALOG = 1,
116 	DC_EDID_CONNECTOR_DIGITAL = 10,
117 	DC_EDID_CONNECTOR_DVI = 11,
118 	DC_EDID_CONNECTOR_HDMIA = 12,
119 	DC_EDID_CONNECTOR_MDDI = 14,
120 	DC_EDID_CONNECTOR_DISPLAYPORT = 15
121 };
122 
123 enum dc_edid_status {
124 	EDID_OK,
125 	EDID_BAD_INPUT,
126 	EDID_NO_RESPONSE,
127 	EDID_BAD_CHECKSUM,
128 	EDID_THE_SAME,
129 	EDID_FALL_BACK,
130 	EDID_PARTIAL_VALID,
131 };
132 
133 enum act_return_status {
134 	ACT_SUCCESS,
135 	ACT_LINK_LOST,
136 	ACT_FAILED
137 };
138 
139 /* audio capability from EDID*/
140 struct dc_cea_audio_mode {
141 	uint8_t format_code; /* ucData[0] [6:3]*/
142 	uint8_t channel_count; /* ucData[0] [2:0]*/
143 	uint8_t sample_rate; /* ucData[1]*/
144 	union {
145 		uint8_t sample_size; /* for LPCM*/
146 		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
147 		uint8_t max_bit_rate;
148 		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
149 	};
150 };
151 
152 struct dc_edid {
153 	uint32_t length;
154 	uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
155 };
156 
157 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
158  * is used. In this case we assume speaker location are: front left, front
159  * right and front center. */
160 #define DEFAULT_SPEAKER_LOCATION 5
161 
162 #define DC_MAX_AUDIO_DESC_COUNT 16
163 
164 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
165 
166 union display_content_support {
167 	unsigned int raw;
168 	struct {
169 		unsigned int valid_content_type :1;
170 		unsigned int game_content :1;
171 		unsigned int cinema_content :1;
172 		unsigned int photo_content :1;
173 		unsigned int graphics_content :1;
174 		unsigned int reserved :27;
175 	} bits;
176 };
177 
178 struct dc_panel_patch {
179 	unsigned int dppowerup_delay;
180 	unsigned int extra_t12_ms;
181 	unsigned int extra_delay_backlight_off;
182 	unsigned int extra_t7_ms;
183 	unsigned int skip_scdc_overwrite;
184 	unsigned int delay_ignore_msa;
185 	unsigned int disable_fec;
186 	unsigned int extra_t3_ms;
187 	unsigned int max_dsc_target_bpp_limit;
188 	unsigned int embedded_tiled_slave;
189 	unsigned int disable_fams;
190 	unsigned int skip_avmute;
191 	unsigned int mst_start_top_delay;
192 };
193 
194 struct dc_edid_caps {
195 	/* sink identification */
196 	uint16_t manufacturer_id;
197 	uint16_t product_id;
198 	uint32_t serial_number;
199 	uint8_t manufacture_week;
200 	uint8_t manufacture_year;
201 	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
202 
203 	/* audio caps */
204 	uint8_t speaker_flags;
205 	uint32_t audio_mode_count;
206 	struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
207 	uint32_t audio_latency;
208 	uint32_t video_latency;
209 
210 	union display_content_support content_support;
211 
212 	uint8_t qs_bit;
213 	uint8_t qy_bit;
214 
215 	uint32_t max_tmds_clk_mhz;
216 
217 	/*HDMI 2.0 caps*/
218 	bool lte_340mcsc_scramble;
219 
220 	bool edid_hdmi;
221 	bool hdr_supported;
222 
223 	struct dc_panel_patch panel_patch;
224 };
225 
226 struct dc_mode_flags {
227 	/* note: part of refresh rate flag*/
228 	uint32_t INTERLACE :1;
229 	/* native display timing*/
230 	uint32_t NATIVE :1;
231 	/* preferred is the recommended mode, one per display */
232 	uint32_t PREFERRED :1;
233 	/* true if this mode should use reduced blanking timings
234 	 *_not_ related to the Reduced Blanking adjustment*/
235 	uint32_t REDUCED_BLANKING :1;
236 	/* note: part of refreshrate flag*/
237 	uint32_t VIDEO_OPTIMIZED_RATE :1;
238 	/* should be reported to upper layers as mode_flags*/
239 	uint32_t PACKED_PIXEL_FORMAT :1;
240 	/*< preferred view*/
241 	uint32_t PREFERRED_VIEW :1;
242 	/* this timing should be used only in tiled mode*/
243 	uint32_t TILED_MODE :1;
244 	uint32_t DSE_MODE :1;
245 	/* Refresh rate divider when Miracast sink is using a
246 	 different rate than the output display device
247 	 Must be zero for wired displays and non-zero for
248 	 Miracast displays*/
249 	uint32_t MIRACAST_REFRESH_DIVIDER;
250 };
251 
252 
253 enum dc_timing_source {
254 	TIMING_SOURCE_UNDEFINED,
255 
256 	/* explicitly specifed by user, most important*/
257 	TIMING_SOURCE_USER_FORCED,
258 	TIMING_SOURCE_USER_OVERRIDE,
259 	TIMING_SOURCE_CUSTOM,
260 	TIMING_SOURCE_EXPLICIT,
261 
262 	/* explicitly specified by the display device, more important*/
263 	TIMING_SOURCE_EDID_CEA_SVD_3D,
264 	TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
265 	TIMING_SOURCE_EDID_CEA_SVD_420,
266 	TIMING_SOURCE_EDID_DETAILED,
267 	TIMING_SOURCE_EDID_ESTABLISHED,
268 	TIMING_SOURCE_EDID_STANDARD,
269 	TIMING_SOURCE_EDID_CEA_SVD,
270 	TIMING_SOURCE_EDID_CVT_3BYTE,
271 	TIMING_SOURCE_EDID_4BYTE,
272 	TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
273 	TIMING_SOURCE_EDID_CEA_RID,
274 	TIMING_SOURCE_VBIOS,
275 	TIMING_SOURCE_CV,
276 	TIMING_SOURCE_TV,
277 	TIMING_SOURCE_HDMI_VIC,
278 
279 	/* implicitly specified by display device, still safe but less important*/
280 	TIMING_SOURCE_DEFAULT,
281 
282 	/* only used for custom base modes */
283 	TIMING_SOURCE_CUSTOM_BASE,
284 
285 	/* these timing might not work, least important*/
286 	TIMING_SOURCE_RANGELIMIT,
287 	TIMING_SOURCE_OS_FORCED,
288 	TIMING_SOURCE_IMPLICIT,
289 
290 	/* only used by default mode list*/
291 	TIMING_SOURCE_BASICMODE,
292 
293 	TIMING_SOURCE_COUNT
294 };
295 
296 
297 struct stereo_3d_features {
298 	bool supported			;
299 	bool allTimings			;
300 	bool cloneMode			;
301 	bool scaling			;
302 	bool singleFrameSWPacked;
303 };
304 
305 enum dc_timing_support_method {
306 	TIMING_SUPPORT_METHOD_UNDEFINED,
307 	TIMING_SUPPORT_METHOD_EXPLICIT,
308 	TIMING_SUPPORT_METHOD_IMPLICIT,
309 	TIMING_SUPPORT_METHOD_NATIVE
310 };
311 
312 struct dc_mode_info {
313 	uint32_t pixel_width;
314 	uint32_t pixel_height;
315 	uint32_t field_rate;
316 	/* Vertical refresh rate for progressive modes.
317 	* Field rate for interlaced modes.*/
318 
319 	enum dc_timing_standard timing_standard;
320 	enum dc_timing_source timing_source;
321 	struct dc_mode_flags flags;
322 };
323 
324 enum dc_power_state {
325 	DC_POWER_STATE_ON = 1,
326 	DC_POWER_STATE_STANDBY,
327 	DC_POWER_STATE_SUSPEND,
328 	DC_POWER_STATE_OFF
329 };
330 
331 /* DC PowerStates */
332 enum dc_video_power_state {
333 	DC_VIDEO_POWER_UNSPECIFIED = 0,
334 	DC_VIDEO_POWER_ON = 1,
335 	DC_VIDEO_POWER_STANDBY,
336 	DC_VIDEO_POWER_SUSPEND,
337 	DC_VIDEO_POWER_OFF,
338 	DC_VIDEO_POWER_HIBERNATE,
339 	DC_VIDEO_POWER_SHUTDOWN,
340 	DC_VIDEO_POWER_ULPS,	/* BACO or Ultra-Light-Power-State */
341 	DC_VIDEO_POWER_AFTER_RESET,
342 	DC_VIDEO_POWER_MAXIMUM
343 };
344 
345 enum dc_acpi_cm_power_state {
346 	DC_ACPI_CM_POWER_STATE_D0 = 1,
347 	DC_ACPI_CM_POWER_STATE_D1 = 2,
348 	DC_ACPI_CM_POWER_STATE_D2 = 4,
349 	DC_ACPI_CM_POWER_STATE_D3 = 8
350 };
351 
352 enum dc_connection_type {
353 	dc_connection_none,
354 	dc_connection_single,
355 	dc_connection_mst_branch,
356 	dc_connection_sst_branch
357 };
358 
359 struct dc_csc_adjustments {
360 	struct fixed31_32 contrast;
361 	struct fixed31_32 saturation;
362 	struct fixed31_32 brightness;
363 	struct fixed31_32 hue;
364 };
365 
366 /* Scaling format */
367 enum scaling_transformation {
368 	SCALING_TRANSFORMATION_UNINITIALIZED,
369 	SCALING_TRANSFORMATION_IDENTITY = 0x0001,
370 	SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
371 	SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
372 	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
373 	SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
374 	SCALING_TRANSFORMATION_INVALID = 0x80000000,
375 
376 	/* Flag the first and last */
377 	SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
378 	SCALING_TRANSFORMATION_END =
379 		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
380 };
381 
382 enum display_content_type {
383 	DISPLAY_CONTENT_TYPE_NO_DATA = 0,
384 	DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
385 	DISPLAY_CONTENT_TYPE_PHOTO = 2,
386 	DISPLAY_CONTENT_TYPE_CINEMA = 4,
387 	DISPLAY_CONTENT_TYPE_GAME = 8
388 };
389 
390 enum cm_gamut_adjust_type {
391 	CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
392 	CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
393 	CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
394 };
395 
396 struct cm_grph_csc_adjustment {
397 	struct fixed31_32 temperature_matrix[12];
398 	enum cm_gamut_adjust_type gamut_adjust_type;
399 	enum cm_gamut_coef_format gamut_coef_format;
400 };
401 
402 /* writeback */
403 struct dwb_stereo_params {
404 	bool				stereo_enabled;		/* false: normal mode, true: 3D stereo */
405 	enum dwb_stereo_type		stereo_type;		/* indicates stereo format */
406 	bool				stereo_polarity;	/* indicates left eye or right eye comes first in stereo mode */
407 	enum dwb_stereo_eye_select	stereo_eye_select;	/* indicate which eye should be captured */
408 };
409 
410 struct dc_dwb_cnv_params {
411 	unsigned int		src_width;	/* input active width */
412 	unsigned int		src_height;	/* input active height (half-active height in interlaced mode) */
413 	unsigned int		crop_width;	/* cropped window width at cnv output */
414 	bool			crop_en;	/* window cropping enable in cnv */
415 	unsigned int		crop_height;	/* cropped window height at cnv output */
416 	unsigned int		crop_x;		/* cropped window start x value at cnv output */
417 	unsigned int		crop_y;		/* cropped window start y value at cnv output */
418 	enum dwb_cnv_out_bpc cnv_out_bpc;	/* cnv output pixel depth - 8bpc or 10bpc */
419 	enum dwb_out_format	fc_out_format;	/* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
420 	enum dwb_out_denorm	out_denorm_mode;/* dwb output denormalization mode */
421 	unsigned int		out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
422 	unsigned int		out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
423 };
424 
425 struct dc_dwb_params {
426 	unsigned int			dwbscl_black_color; /* must be in FP1.5.10 */
427 	unsigned int			hdr_mult;	/* must be in FP1.6.12 */
428 	struct cm_grph_csc_adjustment	csc_params;
429 	struct dwb_stereo_params	stereo_params;
430 	struct dc_dwb_cnv_params	cnv_params;	/* CNV source size and cropping window parameters */
431 	unsigned int			dest_width;	/* Destination width */
432 	unsigned int			dest_height;	/* Destination height */
433 	enum dwb_scaler_mode		out_format;	/* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
434 	enum dwb_output_depth		output_depth;	/* output pixel depth - 8bpc or 10bpc */
435 	enum dwb_capture_rate		capture_rate;	/* controls the frame capture rate */
436 	struct scaling_taps 		scaler_taps;	/* Scaling taps */
437 	enum dwb_subsample_position	subsample_position;
438 	struct dc_transfer_func *out_transfer_func;
439 };
440 
441 /* audio*/
442 
443 union audio_sample_rates {
444 	struct sample_rates {
445 		uint8_t RATE_32:1;
446 		uint8_t RATE_44_1:1;
447 		uint8_t RATE_48:1;
448 		uint8_t RATE_88_2:1;
449 		uint8_t RATE_96:1;
450 		uint8_t RATE_176_4:1;
451 		uint8_t RATE_192:1;
452 	} rate;
453 
454 	uint8_t all;
455 };
456 
457 struct audio_speaker_flags {
458 	uint32_t FL_FR:1;
459 	uint32_t LFE:1;
460 	uint32_t FC:1;
461 	uint32_t RL_RR:1;
462 	uint32_t RC:1;
463 	uint32_t FLC_FRC:1;
464 	uint32_t RLC_RRC:1;
465 	uint32_t SUPPORT_AI:1;
466 };
467 
468 struct audio_speaker_info {
469 	uint32_t ALLSPEAKERS:7;
470 	uint32_t SUPPORT_AI:1;
471 };
472 
473 
474 struct audio_info_flags {
475 
476 	union {
477 
478 		struct audio_speaker_flags speaker_flags;
479 		struct audio_speaker_info   info;
480 
481 		uint8_t all;
482 	};
483 };
484 
485 enum audio_format_code {
486 	AUDIO_FORMAT_CODE_FIRST = 1,
487 	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
488 
489 	AUDIO_FORMAT_CODE_AC3,
490 	/*Layers 1 & 2 */
491 	AUDIO_FORMAT_CODE_MPEG1,
492 	/*MPEG1 Layer 3 */
493 	AUDIO_FORMAT_CODE_MP3,
494 	/*multichannel */
495 	AUDIO_FORMAT_CODE_MPEG2,
496 	AUDIO_FORMAT_CODE_AAC,
497 	AUDIO_FORMAT_CODE_DTS,
498 	AUDIO_FORMAT_CODE_ATRAC,
499 	AUDIO_FORMAT_CODE_1BITAUDIO,
500 	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
501 	AUDIO_FORMAT_CODE_DTS_HD,
502 	AUDIO_FORMAT_CODE_MAT_MLP,
503 	AUDIO_FORMAT_CODE_DST,
504 	AUDIO_FORMAT_CODE_WMAPRO,
505 	AUDIO_FORMAT_CODE_LAST,
506 	AUDIO_FORMAT_CODE_COUNT =
507 		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
508 };
509 
510 struct audio_mode {
511 	 /* ucData[0] [6:3] */
512 	enum audio_format_code format_code;
513 	/* ucData[0] [2:0] */
514 	uint8_t channel_count;
515 	/* ucData[1] */
516 	union audio_sample_rates sample_rates;
517 	union {
518 		/* for LPCM */
519 		uint8_t sample_size;
520 		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
521 		uint8_t max_bit_rate;
522 		/* for Audio Formats 9-15 */
523 		uint8_t vendor_specific;
524 	};
525 };
526 
527 struct audio_info {
528 	struct audio_info_flags flags;
529 	uint32_t video_latency;
530 	uint32_t audio_latency;
531 	uint32_t display_index;
532 	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
533 	uint32_t manufacture_id;
534 	uint32_t product_id;
535 	/* PortID used for ContainerID when defined */
536 	uint32_t port_id[2];
537 	uint32_t mode_count;
538 	/* this field must be last in this struct */
539 	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
540 };
541 struct audio_check {
542 	unsigned int audio_packet_type;
543 	unsigned int max_audiosample_rate;
544 	unsigned int acat;
545 };
546 enum dc_infoframe_type {
547 	DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
548 	DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
549 	DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
550 	DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
551 	DC_DP_INFOFRAME_TYPE_PPS = 0x10,
552 };
553 
554 struct dc_info_packet {
555 	bool valid;
556 	uint8_t hb0;
557 	uint8_t hb1;
558 	uint8_t hb2;
559 	uint8_t hb3;
560 	uint8_t sb[32];
561 };
562 
563 struct dc_info_packet_128 {
564 	bool valid;
565 	uint8_t hb0;
566 	uint8_t hb1;
567 	uint8_t hb2;
568 	uint8_t hb3;
569 	uint8_t sb[128];
570 };
571 
572 #define DC_PLANE_UPDATE_TIMES_MAX 10
573 
574 struct dc_plane_flip_time {
575 	unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
576 	unsigned int index;
577 	unsigned int prev_update_time_in_us;
578 };
579 
580 enum dc_psr_state {
581 	PSR_STATE0 = 0x0,
582 	PSR_STATE1,
583 	PSR_STATE1a,
584 	PSR_STATE2,
585 	PSR_STATE2a,
586 	PSR_STATE2b,
587 	PSR_STATE3,
588 	PSR_STATE3Init,
589 	PSR_STATE4,
590 	PSR_STATE4a,
591 	PSR_STATE4b,
592 	PSR_STATE4c,
593 	PSR_STATE4d,
594 	PSR_STATE4_FULL_FRAME,
595 	PSR_STATE4a_FULL_FRAME,
596 	PSR_STATE4b_FULL_FRAME,
597 	PSR_STATE4c_FULL_FRAME,
598 	PSR_STATE4_FULL_FRAME_POWERUP,
599 	PSR_STATE4_FULL_FRAME_HW_LOCK,
600 	PSR_STATE5,
601 	PSR_STATE5a,
602 	PSR_STATE5b,
603 	PSR_STATE5c,
604 	PSR_STATE_HWLOCK_MGR,
605 	PSR_STATE_POLLVUPDATE,
606 	PSR_STATE_INVALID = 0xFF
607 };
608 
609 struct psr_config {
610 	unsigned char psr_version;
611 	unsigned int psr_rfb_setup_time;
612 	bool psr_exit_link_training_required;
613 	bool psr_frame_capture_indication_req;
614 	unsigned int psr_sdp_transmit_line_num_deadline;
615 	bool allow_smu_optimizations;
616 	bool allow_multi_disp_optimizations;
617 	/* Panel self refresh 2 selective update granularity required */
618 	bool su_granularity_required;
619 	/* psr2 selective update y granularity capability */
620 	uint8_t su_y_granularity;
621 	unsigned int line_time_in_us;
622 	uint8_t rate_control_caps;
623 	uint16_t dsc_slice_height;
624 };
625 
626 union dmcu_psr_level {
627 	struct {
628 		unsigned int SKIP_CRC:1;
629 		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
630 		unsigned int SKIP_PHY_POWER_DOWN:1;
631 		unsigned int SKIP_AUX_ACK_CHECK:1;
632 		unsigned int SKIP_CRTC_DISABLE:1;
633 		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
634 		unsigned int SKIP_SMU_NOTIFICATION:1;
635 		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
636 		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
637 		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
638 		unsigned int DISABLE_ALPM:1;
639 		unsigned int ALPM_DEFAULT_PD_MODE:1;
640 		unsigned int RESERVED:20;
641 	} bits;
642 	unsigned int u32all;
643 };
644 
645 enum physical_phy_id {
646 	PHYLD_0,
647 	PHYLD_1,
648 	PHYLD_2,
649 	PHYLD_3,
650 	PHYLD_4,
651 	PHYLD_5,
652 	PHYLD_6,
653 	PHYLD_7,
654 	PHYLD_8,
655 	PHYLD_9,
656 	PHYLD_COUNT,
657 	PHYLD_UNKNOWN = (-1L)
658 };
659 
660 enum phy_type {
661 	PHY_TYPE_UNKNOWN  = 1,
662 	PHY_TYPE_PCIE_PHY = 2,
663 	PHY_TYPE_UNIPHY = 3,
664 };
665 
666 struct psr_context {
667 	/* ddc line */
668 	enum channel_id channel;
669 	/* Transmitter id */
670 	enum transmitter transmitterId;
671 	/* Engine Id is used for Dig Be source select */
672 	enum engine_id engineId;
673 	/* Controller Id used for Dig Fe source select */
674 	enum controller_id controllerId;
675 	/* Pcie or Uniphy */
676 	enum phy_type phyType;
677 	/* Physical PHY Id used by SMU interpretation */
678 	enum physical_phy_id smuPhyId;
679 	/* Vertical total pixels from crtc timing.
680 	 * This is used for static screen detection.
681 	 * ie. If we want to detect half a frame,
682 	 * we use this to determine the hyst lines.
683 	 */
684 	unsigned int crtcTimingVerticalTotal;
685 	/* PSR supported from panel capabilities and
686 	 * current display configuration
687 	 */
688 	bool psrSupportedDisplayConfig;
689 	/* Whether fast link training is supported by the panel */
690 	bool psrExitLinkTrainingRequired;
691 	/* If RFB setup time is greater than the total VBLANK time,
692 	 * it is not possible for the sink to capture the video frame
693 	 * in the same frame the SDP is sent. In this case,
694 	 * the frame capture indication bit should be set and an extra
695 	 * static frame should be transmitted to the sink.
696 	 */
697 	bool psrFrameCaptureIndicationReq;
698 	/* Set the last possible line SDP may be transmitted without violating
699 	 * the RFB setup time or entering the active video frame.
700 	 */
701 	unsigned int sdpTransmitLineNumDeadline;
702 	/* The VSync rate in Hz used to calculate the
703 	 * step size for smooth brightness feature
704 	 */
705 	unsigned int vsync_rate_hz;
706 	unsigned int skipPsrWaitForPllLock;
707 	unsigned int numberOfControllers;
708 	/* Unused, for future use. To indicate that first changed frame from
709 	 * state3 shouldn't result in psr_inactive, but rather to perform
710 	 * an automatic single frame rfb_update.
711 	 */
712 	bool rfb_update_auto_en;
713 	/* Number of frame before entering static screen */
714 	unsigned int timehyst_frames;
715 	/* Partial frames before entering static screen */
716 	unsigned int hyst_lines;
717 	/* # of repeated AUX transaction attempts to make before
718 	 * indicating failure to the driver
719 	 */
720 	unsigned int aux_repeats;
721 	/* Controls hw blocks to power down during PSR active state */
722 	union dmcu_psr_level psr_level;
723 	/* Controls additional delay after remote frame capture before
724 	 * continuing powerd own
725 	 */
726 	unsigned int frame_delay;
727 	bool allow_smu_optimizations;
728 	bool allow_multi_disp_optimizations;
729 	/* Panel self refresh 2 selective update granularity required */
730 	bool su_granularity_required;
731 	/* psr2 selective update y granularity capability */
732 	uint8_t su_y_granularity;
733 	unsigned int line_time_in_us;
734 	uint8_t rate_control_caps;
735 	uint16_t dsc_slice_height;
736 };
737 
738 struct colorspace_transform {
739 	struct fixed31_32 matrix[12];
740 	bool enable_remap;
741 };
742 
743 enum i2c_mot_mode {
744 	I2C_MOT_UNDEF,
745 	I2C_MOT_TRUE,
746 	I2C_MOT_FALSE
747 };
748 
749 struct AsicStateEx {
750 	unsigned int memoryClock;
751 	unsigned int displayClock;
752 	unsigned int engineClock;
753 	unsigned int maxSupportedDppClock;
754 	unsigned int dppClock;
755 	unsigned int socClock;
756 	unsigned int dcfClockDeepSleep;
757 	unsigned int fClock;
758 	unsigned int phyClock;
759 };
760 
761 
762 enum dc_clock_type {
763 	DC_CLOCK_TYPE_DISPCLK = 0,
764 	DC_CLOCK_TYPE_DPPCLK        = 1,
765 };
766 
767 struct dc_clock_config {
768 	uint32_t max_clock_khz;
769 	uint32_t min_clock_khz;
770 	uint32_t bw_requirequired_clock_khz;
771 	uint32_t current_clock_khz;/*current clock in use*/
772 };
773 
774 struct hw_asic_id {
775 	uint32_t chip_id;
776 	uint32_t chip_family;
777 	uint32_t pci_revision_id;
778 	uint32_t hw_internal_rev;
779 	uint32_t vram_type;
780 	uint32_t vram_width;
781 	uint32_t feature_flags;
782 	uint32_t fake_paths_num;
783 	void *atombios_base_address;
784 };
785 
786 struct dc_context {
787 	struct dc *dc;
788 
789 	void *driver_context; /* e.g. amdgpu_device */
790 	struct dc_perf_trace *perf_trace;
791 	void *cgs_device;
792 
793 	enum dce_environment dce_environment;
794 	struct hw_asic_id asic_id;
795 
796 	/* todo: below should probably move to dc.  to facilitate removal
797 	 * of AS we will store these here
798 	 */
799 	enum dce_version dce_version;
800 	struct dc_bios *dc_bios;
801 	bool created_bios;
802 	struct gpio_service *gpio_service;
803 	uint32_t dc_sink_id_count;
804 	uint32_t dc_stream_id_count;
805 	uint32_t dc_edp_id_count;
806 	uint64_t fbc_gpu_addr;
807 	struct dc_dmub_srv *dmub_srv;
808 	struct cp_psp cp_psp;
809 	uint32_t *dcn_reg_offsets;
810 	uint32_t *nbio_reg_offsets;
811 };
812 
813 /* DSC DPCD capabilities */
814 union dsc_slice_caps1 {
815 	struct {
816 		uint8_t NUM_SLICES_1 : 1;
817 		uint8_t NUM_SLICES_2 : 1;
818 		uint8_t RESERVED : 1;
819 		uint8_t NUM_SLICES_4 : 1;
820 		uint8_t NUM_SLICES_6 : 1;
821 		uint8_t NUM_SLICES_8 : 1;
822 		uint8_t NUM_SLICES_10 : 1;
823 		uint8_t NUM_SLICES_12 : 1;
824 	} bits;
825 	uint8_t raw;
826 };
827 
828 union dsc_slice_caps2 {
829 	struct {
830 		uint8_t NUM_SLICES_16 : 1;
831 		uint8_t NUM_SLICES_20 : 1;
832 		uint8_t NUM_SLICES_24 : 1;
833 		uint8_t RESERVED : 5;
834 	} bits;
835 	uint8_t raw;
836 };
837 
838 union dsc_color_formats {
839 	struct {
840 		uint8_t RGB : 1;
841 		uint8_t YCBCR_444 : 1;
842 		uint8_t YCBCR_SIMPLE_422 : 1;
843 		uint8_t YCBCR_NATIVE_422 : 1;
844 		uint8_t YCBCR_NATIVE_420 : 1;
845 		uint8_t RESERVED : 3;
846 	} bits;
847 	uint8_t raw;
848 };
849 
850 union dsc_color_depth {
851 	struct {
852 		uint8_t RESERVED1 : 1;
853 		uint8_t COLOR_DEPTH_8_BPC : 1;
854 		uint8_t COLOR_DEPTH_10_BPC : 1;
855 		uint8_t COLOR_DEPTH_12_BPC : 1;
856 		uint8_t RESERVED2 : 3;
857 	} bits;
858 	uint8_t raw;
859 };
860 
861 struct dsc_dec_dpcd_caps {
862 	bool is_dsc_supported;
863 	uint8_t dsc_version;
864 	int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
865 	union dsc_slice_caps1 slice_caps1;
866 	union dsc_slice_caps2 slice_caps2;
867 	int32_t lb_bit_depth;
868 	bool is_block_pred_supported;
869 	int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
870 	union dsc_color_formats color_formats;
871 	union dsc_color_depth color_depth;
872 	int32_t throughput_mode_0_mps; /* In MPs */
873 	int32_t throughput_mode_1_mps; /* In MPs */
874 	int32_t max_slice_width;
875 	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
876 
877 	/* Extended DSC caps */
878 	uint32_t branch_overall_throughput_0_mps; /* In MPs */
879 	uint32_t branch_overall_throughput_1_mps; /* In MPs */
880 	uint32_t branch_max_line_width;
881 	bool is_dp; /* Decoded format */
882 };
883 
884 struct dc_golden_table {
885 	uint16_t dc_golden_table_ver;
886 	uint32_t aux_dphy_rx_control0_val;
887 	uint32_t aux_dphy_tx_control_val;
888 	uint32_t aux_dphy_rx_control1_val;
889 	uint32_t dc_gpio_aux_ctrl_0_val;
890 	uint32_t dc_gpio_aux_ctrl_1_val;
891 	uint32_t dc_gpio_aux_ctrl_2_val;
892 	uint32_t dc_gpio_aux_ctrl_3_val;
893 	uint32_t dc_gpio_aux_ctrl_4_val;
894 	uint32_t dc_gpio_aux_ctrl_5_val;
895 };
896 
897 enum dc_gpu_mem_alloc_type {
898 	DC_MEM_ALLOC_TYPE_GART,
899 	DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
900 	DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
901 	DC_MEM_ALLOC_TYPE_AGP
902 };
903 
904 enum dc_link_encoding_format {
905 	DC_LINK_ENCODING_UNSPECIFIED = 0,
906 	DC_LINK_ENCODING_DP_8b_10b,
907 	DC_LINK_ENCODING_DP_128b_132b,
908 	DC_LINK_ENCODING_HDMI_TMDS,
909 	DC_LINK_ENCODING_HDMI_FRL
910 };
911 
912 enum dc_psr_version {
913 	DC_PSR_VERSION_1			= 0,
914 	DC_PSR_VERSION_SU_1			= 1,
915 	DC_PSR_VERSION_UNSUPPORTED		= 0xFFFFFFFF,
916 };
917 
918 /* Possible values of display_endpoint_id.endpoint */
919 enum display_endpoint_type {
920 	DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
921 	DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */
922 	DISPLAY_ENDPOINT_UNKNOWN = -1
923 };
924 
925 /* Extends graphics_object_id with an additional member 'ep_type' for
926  * distinguishing between physical endpoints (with entries in BIOS connector table) and
927  * logical endpoints.
928  */
929 struct display_endpoint_id {
930 	struct graphics_object_id link_id;
931 	enum display_endpoint_type ep_type;
932 };
933 
934 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
935 struct otg_phy_mux {
936 	uint8_t phy_output_num;
937 	uint8_t otg_output_num;
938 };
939 #endif
940 
941 enum dc_detect_reason {
942 	DETECT_REASON_BOOT,
943 	DETECT_REASON_RESUMEFROMS3S4,
944 	DETECT_REASON_HPD,
945 	DETECT_REASON_HPDRX,
946 	DETECT_REASON_FALLBACK,
947 	DETECT_REASON_RETRAIN,
948 	DETECT_REASON_TDR,
949 };
950 
951 struct dc_link_status {
952 	bool link_active;
953 	struct dpcd_caps *dpcd_caps;
954 };
955 
956 union hdcp_rx_caps {
957 	struct {
958 		uint8_t version;
959 		uint8_t reserved;
960 		struct {
961 			uint8_t repeater	: 1;
962 			uint8_t hdcp_capable	: 1;
963 			uint8_t reserved	: 6;
964 		} byte0;
965 	} fields;
966 	uint8_t raw[3];
967 };
968 
969 union hdcp_bcaps {
970 	struct {
971 		uint8_t HDCP_CAPABLE:1;
972 		uint8_t REPEATER:1;
973 		uint8_t RESERVED:6;
974 	} bits;
975 	uint8_t raw;
976 };
977 
978 struct hdcp_caps {
979 	union hdcp_rx_caps rx_caps;
980 	union hdcp_bcaps bcaps;
981 };
982 
983 /* DP MST stream allocation (payload bandwidth number) */
984 struct link_mst_stream_allocation {
985 	/* DIG front */
986 	const struct stream_encoder *stream_enc;
987 	/* HPO DP Stream Encoder */
988 	const struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
989 	/* associate DRM payload table with DC stream encoder */
990 	uint8_t vcp_id;
991 	/* number of slots required for the DP stream in transport packet */
992 	uint8_t slot_count;
993 };
994 
995 #define MAX_CONTROLLER_NUM 6
996 
997 /* DP MST stream allocation table */
998 struct link_mst_stream_allocation_table {
999 	/* number of DP video streams */
1000 	int stream_count;
1001 	/* array of stream allocations */
1002 	struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
1003 };
1004 
1005 struct backlight_settings {
1006 	uint32_t backlight_millinits;
1007 };
1008 
1009 /* PSR feature flags */
1010 struct psr_settings {
1011 	bool psr_feature_enabled;		// PSR is supported by sink
1012 	bool psr_allow_active;			// PSR is currently active
1013 	enum dc_psr_version psr_version;		// Internal PSR version, determined based on DPCD
1014 	bool psr_vtotal_control_support;	// Vtotal control is supported by sink
1015 	unsigned long long psr_dirty_rects_change_timestamp_ns;	// for delay of enabling PSR-SU
1016 
1017 	/* These parameters are calculated in Driver,
1018 	 * based on display timing and Sink capabilities.
1019 	 * If VBLANK region is too small and Sink takes a long time
1020 	 * to set up RFB, it may take an extra frame to enter PSR state.
1021 	 */
1022 	bool psr_frame_capture_indication_req;
1023 	unsigned int psr_sdp_transmit_line_num_deadline;
1024 	uint8_t force_ffu_mode;
1025 	unsigned int psr_power_opt;
1026 };
1027 
1028 enum replay_coasting_vtotal_type {
1029 	PR_COASTING_TYPE_NOM = 0,
1030 	PR_COASTING_TYPE_STATIC,
1031 	PR_COASTING_TYPE_FULL_SCREEN_VIDEO,
1032 	PR_COASTING_TYPE_TEST_HARNESS,
1033 	PR_COASTING_TYPE_NUM,
1034 };
1035 
1036 union replay_error_status {
1037 	struct {
1038 		unsigned char STATE_TRANSITION_ERROR    :1;
1039 		unsigned char LINK_CRC_ERROR            :1;
1040 		unsigned char DESYNC_ERROR              :1;
1041 		unsigned char RESERVED                  :5;
1042 	} bits;
1043 	unsigned char raw;
1044 };
1045 
1046 struct replay_config {
1047 	bool replay_supported;                          // Replay feature is supported
1048 	unsigned int replay_power_opt_supported;        // Power opt flags that are supported
1049 	bool replay_smu_opt_supported;                  // SMU optimization is supported
1050 	unsigned int replay_enable_option;              // Replay enablement option
1051 	uint32_t debug_flags;                           // Replay debug flags
1052 	bool replay_timing_sync_supported;             // Replay desync is supported
1053 	union replay_error_status replay_error_status; // Replay error status
1054 };
1055 
1056 /* Replay feature flags */
1057 struct replay_settings {
1058 	struct replay_config config;            // Replay configuration
1059 	bool replay_feature_enabled;            // Replay feature is ready for activating
1060 	bool replay_allow_active;               // Replay is currently active
1061 	unsigned int replay_power_opt_active;   // Power opt flags that are activated currently
1062 	bool replay_smu_opt_enable;             // SMU optimization is enabled
1063 	uint16_t coasting_vtotal;               // Current Coasting vtotal
1064 	uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; // Coasting vtotal table
1065 };
1066 
1067 /* To split out "global" and "per-panel" config settings.
1068  * Add a struct dc_panel_config under dc_link
1069  */
1070 struct dc_panel_config {
1071 	/* extra panel power sequence parameters */
1072 	struct pps {
1073 		unsigned int extra_t3_ms;
1074 		unsigned int extra_t7_ms;
1075 		unsigned int extra_delay_backlight_off;
1076 		unsigned int extra_post_t7_ms;
1077 		unsigned int extra_pre_t11_ms;
1078 		unsigned int extra_t12_ms;
1079 		unsigned int extra_post_OUI_ms;
1080 	} pps;
1081 	/* nit brightness */
1082 	struct nits_brightness {
1083 		unsigned int peak; /* nits */
1084 		unsigned int max_avg; /* nits */
1085 		unsigned int min; /* 1/10000 nits */
1086 		unsigned int max_nonboost_brightness_millinits;
1087 		unsigned int min_brightness_millinits;
1088 	} nits_brightness;
1089 	/* PSR */
1090 	struct psr {
1091 		bool disable_psr;
1092 		bool disallow_psrsu;
1093 		bool disallow_replay;
1094 		bool rc_disable;
1095 		bool rc_allow_static_screen;
1096 		bool rc_allow_fullscreen_VPB;
1097 		unsigned int replay_enable_option;
1098 	} psr;
1099 	/* ABM */
1100 	struct varib {
1101 		unsigned int varibright_feature_enable;
1102 		unsigned int def_varibright_level;
1103 		unsigned int abm_config_setting;
1104 	} varib;
1105 	/* edp DSC */
1106 	struct dsc {
1107 		bool disable_dsc_edp;
1108 		unsigned int force_dsc_edp_policy;
1109 	} dsc;
1110 	/* eDP ILR */
1111 	struct ilr {
1112 		bool optimize_edp_link_rate; /* eDP ILR */
1113 	} ilr;
1114 };
1115 
1116 /*
1117  *  USB4 DPIA BW ALLOCATION STRUCTS
1118  */
1119 struct dc_dpia_bw_alloc {
1120 	int sink_verified_bw;  // The Verified BW that sink can allocated and use that has been verified already
1121 	int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated
1122 	int sink_max_bw;       // The Max BW that sink can require/support
1123 	int estimated_bw;      // The estimated available BW for this DPIA
1124 	int bw_granularity;    // BW Granularity
1125 	bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3:  DP-Tx & Dpia & CM
1126 	bool response_ready;   // Response ready from the CM side
1127 };
1128 
1129 #define MAX_SINKS_PER_LINK 4
1130 
1131 enum dc_hpd_enable_select {
1132 	HPD_EN_FOR_ALL_EDP = 0,
1133 	HPD_EN_FOR_PRIMARY_EDP_ONLY,
1134 	HPD_EN_FOR_SECONDARY_EDP_ONLY,
1135 };
1136 
1137 #endif /* DC_TYPES_H_ */
1138