Searched refs:DATA_SEL (Results 1 – 16 of 16) sorted by relevance
190 #define DATA_SEL(x) ((x) << 29) macro
249 #define DATA_SEL(x) ((x) << 29) macro
367 #define DATA_SEL(x) ((x) << 29) macro
2130 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()2142 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()2171 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
1826 #define DATA_SEL(x) ((x) << 29) macro
6168 DATA_SEL(1) | INT_SEL(0)); in gfx_v8_0_ring_emit_fence_gfx()6182 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()6259 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
2559 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_4_3_ring_emit_fence()
5303 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
1249 #define DATA_SEL(x) ((x) << 29) macro
1763 #define DATA_SEL(x) ((x) << 29) macro
1835 #define DATA_SEL(x) ((x) << 29) macro
1407 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
1674 #define DATA_SEL(x) ((x) << 29) macro
3556 DATA_SEL(1) | INT_SEL(0)); in cik_fence_gfx_ring_emit()3567 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()3593 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
2889 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
3391 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()
