Searched refs:Chipset (Results 1 – 18 of 18) sorted by relevance
22 7 Series Chipset Family23 6 Series Chipset Family24 5 Series Chipset Family25 4 Series Chipset Family26 Mobile 4 Series Chipset Family
152 if (((par->Chipset & 0xfff0) == 0x0290) || in nvGetClocks()153 ((par->Chipset & 0xfff0) == 0x0390)) { in nvGetClocks()200 if (((par->Chipset & 0x0ff0) == 0x0300) || in nvGetClocks()201 ((par->Chipset & 0x0ff0) == 0x0330)) { in nvGetClocks()688 if ((par->Chipset & 0x0FF0) == 0x01A0) { in nForceUpdateArbitrationSettings()904 if ((par->Chipset & 0xfff0) == 0x0240 || in NVCalcStateExt()905 (par->Chipset & 0xfff0) == 0x03d0) { in NVCalcStateExt()908 } else if (((par->Chipset & 0xffff) == 0x01A0) || in NVCalcStateExt()909 ((par->Chipset & 0xffff) == 0x01f0)) { in NVCalcStateExt()963 (par->Chipset & 0xfff0) == 0x0040) { in NVLoadStateExt()[all …]
230 u32 implementation = par->Chipset & 0x0ff0; in nv10GetConfig()242 if ((par->Chipset & 0xffff) == 0x01a0) { in nv10GetConfig()247 } else if ((par->Chipset & 0xffff) == 0x01f0) { in nv10GetConfig()275 u16 implementation = par->Chipset & 0x0ff0; in NVCommonSetup()325 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020); in NVCommonSetup()328 switch (par->Chipset & 0xffff) { in NVCommonSetup()408 if ((par->Chipset & 0x0fff) <= 0x0020) in NVCommonSetup()
177 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { in nvidia_panel_tweak()182 if ((par->Chipset & 0xfff0) == 0x0310) in nvidia_panel_tweak()462 if ((par->Chipset & 0x0ff0) != 0x0110) in nvidia_calc_regs()471 if ((par->Chipset & 0x0ff0) == 0x0110) { in nvidia_calc_regs()619 if ((par->Chipset & 0x0ff0) == 0x0110) in nvidiafb_set_par()1225 static u32 nvidia_get_arch(u32 Chipset) in nvidia_get_arch() argument1229 switch (Chipset & 0x0ff0) { in nvidia_get_arch()1283 int Chipset; in nvidiafb_probe() local1308 Chipset = nvidia_get_chipset(pd, REGS); in nvidiafb_probe()1309 Architecture = nvidia_get_arch(Chipset); in nvidiafb_probe()[all …]
106 int Chipset; member
103 switch(par->Chipset & 0xffff) { in riva_is_second()159 unsigned int chipset = par->Chipset; in riva_get_memlen()341 switch (par->Chipset & 0xffff) { in riva_common_setup()377 switch (par->Chipset & 0x0ff0) { in riva_common_setup()379 if (par->Chipset == NV_CHIP_GEFORCE2_GO) in riva_common_setup()421 RivaGetConfig(&par->riva, par->pdev, par->Chipset); in riva_common_setup()
59 unsigned int Chipset; member
1278 if((chip->Chipset == NV_CHIP_IGEFORCE2) || in CalcStateExt()1279 (chip->Chipset == NV_CHIP_0x01F0)) in CalcStateExt()1627 if((chip->Chipset & 0x0ff0) == 0x0110) { in LoadStateExt()1630 if((chip->Chipset & 0x0ff0) >= 0x0170) { in LoadStateExt()1783 if((chip->Chipset & 0x0ff0) == 0x0110) { in UnloadStateExt()1786 if((chip->Chipset & 0x0ff0) >= 0x0170) { in UnloadStateExt()2220 chip->Chipset = chipset; in RivaGetConfig()
428 U032 Chipset; member
1928 default_par->Chipset = (pd->vendor << 16) | pd->device; in rivafb_probe()1929 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); in rivafb_probe()
42 1. Chipset (PCH) temperature49 8. Chipset fan RPM
61 * Chipset Temperature,
260 - 5 indicates Chipset fan
6 SCU controller. The Intel(R) C600 Series Chipset SATA/SAS
625 ICU02F0 "Gateway Ethertwist 16 (Fujitsu Chipset)"626 ICU02F1 "Gateway Ethertwist 16 (National Chipset)"627 ICU0300 "Gateway Ethertwist PC/PC-WS(National Chipset)"
12 SoC/Chipset to appear only in ACPI namespace. These are typically devices
679 tristate "Intel(R) C600 Series Chipset SAS Controller"
1545 D: Active-ATA-Chipset maddness..........
