| /Linux-v6.6/drivers/scsi/aacraid/ |
| D | aacraid.h | 1083 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1084 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
1085 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
1086 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
1145 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
1146 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
1147 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
1148 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
1163 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
1164 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
|
| /Linux-v6.6/drivers/dma/ |
| D | txx9dmac.c | 296 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
308 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
339 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
349 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
370 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
519 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
545 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
546 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
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| D | txx9dmac.h | 78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
88 u32 CSR; member
|
| /Linux-v6.6/Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 36 - reg : shall be a list of address and length pairs describing the CSR
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
|
| /Linux-v6.6/drivers/staging/qlge/ |
| D | qlge_mpi.c | 9 tmp = qlge_read32(qdev, CSR); in qlge_unpause_mpi_risc()
13 qlge_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in qlge_unpause_mpi_risc()
23 qlge_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in qlge_pause_mpi_risc()
25 tmp = qlge_read32(qdev, CSR); in qlge_pause_mpi_risc()
39 qlge_write32(qdev, CSR, CSR_CMD_SET_RST); in qlge_hard_reset_mpi_risc()
41 tmp = qlge_read32(qdev, CSR); in qlge_hard_reset_mpi_risc()
43 qlge_write32(qdev, CSR, CSR_CMD_CLR_RST); in qlge_hard_reset_mpi_risc()
170 if (qlge_read32(qdev, CSR) & CSR_HRI) in qlge_exec_mb_cmd()
189 qlge_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in qlge_exec_mb_cmd()
513 qlge_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in qlge_mpi_handler()
[all …]
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| /Linux-v6.6/Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 151 - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
|
| D | introduction.rst | 262 直接映射虚拟内存通过CSR.DMWn（n=0~3）来进行配置，虚拟地址（VA）和物理地址（PA）
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| /Linux-v6.6/drivers/soc/litex/ |
| D | Kconfig | 15 LiteX CSR access and provides common litex_[read|write]*
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| /Linux-v6.6/Documentation/devicetree/bindings/pci/ |
| D | altera-pcie-msi.txt | 8 "csr": CSR registers
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| D | mediatek-pcie.txt | 24 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
|
| /Linux-v6.6/arch/arm/mach-omap1/ |
| D | dma.c | 59 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
219 l = dma_read(CSR, lch); in omap1_clear_dma()
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| D | omap-dma.c | 87 p->dma_read(CSR, lch); in omap_disable_channel_irq()
325 p->dma_read(CSR, lch); in omap_enable_channel_irq()
711 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
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| /Linux-v6.6/Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 149 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
|
| /Linux-v6.6/arch/arm/mach-omap2/ |
| D | dma.c | 57 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
|
| /Linux-v6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-sirf.txt | 1 CSR SiRFprimaII pinmux controller
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| /Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
|
| /Linux-v6.6/Documentation/admin-guide/perf/ |
| D | xgene-pmu.rst | 9 interrupt and status CSR region.
|
| /Linux-v6.6/Documentation/arch/arm/ |
| D | ixp4xx.rst | 39 require the use of Intel's proprietary CSR software:
140 the CSR or a WiFi card and a ramdisk that BOOTPs and then does
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| /Linux-v6.6/include/linux/ |
| D | omap-dma.h | 153 CSDP, CCR, CICR, CSR, enumerator
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| /Linux-v6.6/Documentation/driver-api/rapidio/ |
| D | rapidio.rst | 256 device by writing into the Host Device ID Lock CSR. It does this to ensure that
262 is written into the device's Base Device ID CSR.
279 into device's Component Tag CSR. That unique value is used by the error
291 in the system, it sets the Discovered bit in the Port General Control CSR
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| /Linux-v6.6/drivers/misc/eeprom/ |
| D | Kconfig | 114 tristate "IDT 89HPESx PCIe-swtiches EEPROM / CSR support"
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| /Linux-v6.6/drivers/dma/ti/ |
| D | omap-dma.c | 386 omap_dma_chan_read(c, CSR); in omap_dma_clear_csr()
388 omap_dma_chan_write(c, CSR, ~0); in omap_dma_clear_csr()
393 unsigned val = omap_dma_chan_read(c, CSR); in omap_dma_get_csr()
396 omap_dma_chan_write(c, CSR, val); in omap_dma_get_csr()
|
| /Linux-v6.6/arch/arm/mach-tegra/ |
| D | sleep-tegra30.S | 235 ldr r3, [r1] @ read CSR
236 str r3, [r1] @ clear CSR
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| /Linux-v6.6/Documentation/devicetree/bindings/net/ |
| D | snps,dwc-qos-ethernet.txt | 43 The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
|
| /Linux-v6.6/Documentation/riscv/ |
| D | boot.rst | 29 CSR state
|
