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Searched refs:CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT (Results 1 – 13 of 13) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h3179 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d macro
Dgfx_7_2_sh_mask.h2588 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d macro
Dgfx_8_0_sh_mask.h3152 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d macro
Dgfx_8_1_sh_mask.h3674 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h19405 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_9_2_1_sh_mask.h20643 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_9_4_3_sh_mask.h22771 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_9_1_sh_mask.h20716 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_9_4_2_sh_mask.h12870 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_11_0_0_sh_mask.h26793 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_10_1_0_sh_mask.h27318 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_11_0_3_sh_mask.h29293 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
Dgc_10_3_0_sh_mask.h25579 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro