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Searched refs:CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2184 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v6_0_cp_compute_resume()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2782 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L macro
Dgfx_7_2_sh_mask.h1107 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
Dgfx_8_0_sh_mask.h1423 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
Dgfx_8_1_sh_mask.h1947 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h10967 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_1_sh_mask.h12448 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_2_1_sh_mask.h12252 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_4_3_sh_mask.h13977 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_9_4_2_sh_mask.h2268 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_10_1_0_sh_mask.h17912 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … macro
Dgc_10_3_0_sh_mask.h16176 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK … macro