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Searched refs:CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT (Results 1 – 11 of 11) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h3122 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 macro
Dgfx_8_1_sh_mask.h3644 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h19370 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_9_2_1_sh_mask.h20608 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_9_4_3_sh_mask.h22736 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_9_1_sh_mask.h20681 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_9_4_2_sh_mask.h12835 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_11_0_0_sh_mask.h26753 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_10_1_0_sh_mask.h27283 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_11_0_3_sh_mask.h29253 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro
Dgc_10_3_0_sh_mask.h25544 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT … macro