1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006, 2007 Eugene Konev
4 *
5 */
6
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/moduleparam.h>
10
11 #include <linux/sched.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17
18 #include <linux/netdevice.h>
19 #include <linux/if_vlan.h>
20 #include <linux/etherdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/skbuff.h>
23 #include <linux/mii.h>
24 #include <linux/phy.h>
25 #include <linux/phy_fixed.h>
26 #include <linux/platform_device.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/clk.h>
29 #include <linux/gpio.h>
30 #include <linux/atomic.h>
31
32 #include <asm/mach-ar7/ar7.h>
33
34 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
35 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
36 MODULE_LICENSE("GPL");
37 MODULE_ALIAS("platform:cpmac");
38
39 static int debug_level = 8;
40 static int dumb_switch;
41
42 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
43 module_param(debug_level, int, 0444);
44 module_param(dumb_switch, int, 0444);
45
46 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
47 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
48
49 #define CPMAC_VERSION "0.5.2"
50 /* frame size + 802.1q tag + FCS size */
51 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
52 #define CPMAC_QUEUES 8
53
54 /* Ethernet registers */
55 #define CPMAC_TX_CONTROL 0x0004
56 #define CPMAC_TX_TEARDOWN 0x0008
57 #define CPMAC_RX_CONTROL 0x0014
58 #define CPMAC_RX_TEARDOWN 0x0018
59 #define CPMAC_MBP 0x0100
60 #define MBP_RXPASSCRC 0x40000000
61 #define MBP_RXQOS 0x20000000
62 #define MBP_RXNOCHAIN 0x10000000
63 #define MBP_RXCMF 0x01000000
64 #define MBP_RXSHORT 0x00800000
65 #define MBP_RXCEF 0x00400000
66 #define MBP_RXPROMISC 0x00200000
67 #define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
68 #define MBP_RXBCAST 0x00002000
69 #define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
70 #define MBP_RXMCAST 0x00000020
71 #define MBP_MCASTCHAN(channel) ((channel) & 0x7)
72 #define CPMAC_UNICAST_ENABLE 0x0104
73 #define CPMAC_UNICAST_CLEAR 0x0108
74 #define CPMAC_MAX_LENGTH 0x010c
75 #define CPMAC_BUFFER_OFFSET 0x0110
76 #define CPMAC_MAC_CONTROL 0x0160
77 #define MAC_TXPTYPE 0x00000200
78 #define MAC_TXPACE 0x00000040
79 #define MAC_MII 0x00000020
80 #define MAC_TXFLOW 0x00000010
81 #define MAC_RXFLOW 0x00000008
82 #define MAC_MTEST 0x00000004
83 #define MAC_LOOPBACK 0x00000002
84 #define MAC_FDX 0x00000001
85 #define CPMAC_MAC_STATUS 0x0164
86 #define MAC_STATUS_QOS 0x00000004
87 #define MAC_STATUS_RXFLOW 0x00000002
88 #define MAC_STATUS_TXFLOW 0x00000001
89 #define CPMAC_TX_INT_ENABLE 0x0178
90 #define CPMAC_TX_INT_CLEAR 0x017c
91 #define CPMAC_MAC_INT_VECTOR 0x0180
92 #define MAC_INT_STATUS 0x00080000
93 #define MAC_INT_HOST 0x00040000
94 #define MAC_INT_RX 0x00020000
95 #define MAC_INT_TX 0x00010000
96 #define CPMAC_MAC_EOI_VECTOR 0x0184
97 #define CPMAC_RX_INT_ENABLE 0x0198
98 #define CPMAC_RX_INT_CLEAR 0x019c
99 #define CPMAC_MAC_INT_ENABLE 0x01a8
100 #define CPMAC_MAC_INT_CLEAR 0x01ac
101 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
102 #define CPMAC_MAC_ADDR_MID 0x01d0
103 #define CPMAC_MAC_ADDR_HI 0x01d4
104 #define CPMAC_MAC_HASH_LO 0x01d8
105 #define CPMAC_MAC_HASH_HI 0x01dc
106 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
107 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
108 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
109 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
110 #define CPMAC_REG_END 0x0680
111
112 /* Rx/Tx statistics
113 * TODO: use some of them to fill stats in cpmac_stats()
114 */
115 #define CPMAC_STATS_RX_GOOD 0x0200
116 #define CPMAC_STATS_RX_BCAST 0x0204
117 #define CPMAC_STATS_RX_MCAST 0x0208
118 #define CPMAC_STATS_RX_PAUSE 0x020c
119 #define CPMAC_STATS_RX_CRC 0x0210
120 #define CPMAC_STATS_RX_ALIGN 0x0214
121 #define CPMAC_STATS_RX_OVER 0x0218
122 #define CPMAC_STATS_RX_JABBER 0x021c
123 #define CPMAC_STATS_RX_UNDER 0x0220
124 #define CPMAC_STATS_RX_FRAG 0x0224
125 #define CPMAC_STATS_RX_FILTER 0x0228
126 #define CPMAC_STATS_RX_QOSFILTER 0x022c
127 #define CPMAC_STATS_RX_OCTETS 0x0230
128
129 #define CPMAC_STATS_TX_GOOD 0x0234
130 #define CPMAC_STATS_TX_BCAST 0x0238
131 #define CPMAC_STATS_TX_MCAST 0x023c
132 #define CPMAC_STATS_TX_PAUSE 0x0240
133 #define CPMAC_STATS_TX_DEFER 0x0244
134 #define CPMAC_STATS_TX_COLLISION 0x0248
135 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
136 #define CPMAC_STATS_TX_MULTICOLL 0x0250
137 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
138 #define CPMAC_STATS_TX_LATECOLL 0x0258
139 #define CPMAC_STATS_TX_UNDERRUN 0x025c
140 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
141 #define CPMAC_STATS_TX_OCTETS 0x0264
142
143 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
144 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
145 (reg)))
146
147 /* MDIO bus */
148 #define CPMAC_MDIO_VERSION 0x0000
149 #define CPMAC_MDIO_CONTROL 0x0004
150 #define MDIOC_IDLE 0x80000000
151 #define MDIOC_ENABLE 0x40000000
152 #define MDIOC_PREAMBLE 0x00100000
153 #define MDIOC_FAULT 0x00080000
154 #define MDIOC_FAULTDETECT 0x00040000
155 #define MDIOC_INTTEST 0x00020000
156 #define MDIOC_CLKDIV(div) ((div) & 0xff)
157 #define CPMAC_MDIO_ALIVE 0x0008
158 #define CPMAC_MDIO_LINK 0x000c
159 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
160 #define MDIO_BUSY 0x80000000
161 #define MDIO_WRITE 0x40000000
162 #define MDIO_REG(reg) (((reg) & 0x1f) << 21)
163 #define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
164 #define MDIO_DATA(data) ((data) & 0xffff)
165 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
166 #define PHYSEL_LINKSEL 0x00000040
167 #define PHYSEL_LINKINT 0x00000020
168
169 struct cpmac_desc {
170 u32 hw_next;
171 u32 hw_data;
172 u16 buflen;
173 u16 bufflags;
174 u16 datalen;
175 u16 dataflags;
176 #define CPMAC_SOP 0x8000
177 #define CPMAC_EOP 0x4000
178 #define CPMAC_OWN 0x2000
179 #define CPMAC_EOQ 0x1000
180 struct sk_buff *skb;
181 struct cpmac_desc *next;
182 struct cpmac_desc *prev;
183 dma_addr_t mapping;
184 dma_addr_t data_mapping;
185 };
186
187 struct cpmac_priv {
188 spinlock_t lock;
189 spinlock_t rx_lock;
190 struct cpmac_desc *rx_head;
191 int ring_size;
192 struct cpmac_desc *desc_ring;
193 dma_addr_t dma_ring;
194 void __iomem *regs;
195 struct mii_bus *mii_bus;
196 char phy_name[MII_BUS_ID_SIZE + 3];
197 int oldlink, oldspeed, oldduplex;
198 u32 msg_enable;
199 struct net_device *dev;
200 struct work_struct reset_work;
201 struct platform_device *pdev;
202 struct napi_struct napi;
203 atomic_t reset_pending;
204 };
205
206 static irqreturn_t cpmac_irq(int, void *);
207 static void cpmac_hw_start(struct net_device *dev);
208 static void cpmac_hw_stop(struct net_device *dev);
209 static int cpmac_stop(struct net_device *dev);
210 static int cpmac_open(struct net_device *dev);
211
cpmac_dump_regs(struct net_device * dev)212 static void cpmac_dump_regs(struct net_device *dev)
213 {
214 int i;
215 struct cpmac_priv *priv = netdev_priv(dev);
216
217 for (i = 0; i < CPMAC_REG_END; i += 4) {
218 if (i % 16 == 0) {
219 if (i)
220 printk("\n");
221 printk("%s: reg[%p]:", dev->name, priv->regs + i);
222 }
223 printk(" %08x", cpmac_read(priv->regs, i));
224 }
225 printk("\n");
226 }
227
cpmac_dump_desc(struct net_device * dev,struct cpmac_desc * desc)228 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
229 {
230 int i;
231
232 printk("%s: desc[%p]:", dev->name, desc);
233 for (i = 0; i < sizeof(*desc) / 4; i++)
234 printk(" %08x", ((u32 *)desc)[i]);
235 printk("\n");
236 }
237
cpmac_dump_all_desc(struct net_device * dev)238 static void cpmac_dump_all_desc(struct net_device *dev)
239 {
240 struct cpmac_priv *priv = netdev_priv(dev);
241 struct cpmac_desc *dump = priv->rx_head;
242
243 do {
244 cpmac_dump_desc(dev, dump);
245 dump = dump->next;
246 } while (dump != priv->rx_head);
247 }
248
cpmac_dump_skb(struct net_device * dev,struct sk_buff * skb)249 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
250 {
251 int i;
252
253 printk("%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
254 for (i = 0; i < skb->len; i++) {
255 if (i % 16 == 0) {
256 if (i)
257 printk("\n");
258 printk("%s: data[%p]:", dev->name, skb->data + i);
259 }
260 printk(" %02x", ((u8 *)skb->data)[i]);
261 }
262 printk("\n");
263 }
264
cpmac_mdio_read(struct mii_bus * bus,int phy_id,int reg)265 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
266 {
267 u32 val;
268
269 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
270 cpu_relax();
271 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
272 MDIO_PHY(phy_id));
273 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
274 cpu_relax();
275
276 return MDIO_DATA(val);
277 }
278
cpmac_mdio_write(struct mii_bus * bus,int phy_id,int reg,u16 val)279 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
280 int reg, u16 val)
281 {
282 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
283 cpu_relax();
284 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
285 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
286
287 return 0;
288 }
289
cpmac_mdio_reset(struct mii_bus * bus)290 static int cpmac_mdio_reset(struct mii_bus *bus)
291 {
292 struct clk *cpmac_clk;
293
294 cpmac_clk = clk_get(&bus->dev, "cpmac");
295 if (IS_ERR(cpmac_clk)) {
296 pr_err("unable to get cpmac clock\n");
297 return -1;
298 }
299 ar7_device_reset(AR7_RESET_BIT_MDIO);
300 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
301 MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
302
303 return 0;
304 }
305
306 static struct mii_bus *cpmac_mii;
307
cpmac_set_multicast_list(struct net_device * dev)308 static void cpmac_set_multicast_list(struct net_device *dev)
309 {
310 struct netdev_hw_addr *ha;
311 u8 tmp;
312 u32 mbp, bit, hash[2] = { 0, };
313 struct cpmac_priv *priv = netdev_priv(dev);
314
315 mbp = cpmac_read(priv->regs, CPMAC_MBP);
316 if (dev->flags & IFF_PROMISC) {
317 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
318 MBP_RXPROMISC);
319 } else {
320 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
321 if (dev->flags & IFF_ALLMULTI) {
322 /* enable all multicast mode */
323 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
324 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
325 } else {
326 /* cpmac uses some strange mac address hashing
327 * (not crc32)
328 */
329 netdev_for_each_mc_addr(ha, dev) {
330 bit = 0;
331 tmp = ha->addr[0];
332 bit ^= (tmp >> 2) ^ (tmp << 4);
333 tmp = ha->addr[1];
334 bit ^= (tmp >> 4) ^ (tmp << 2);
335 tmp = ha->addr[2];
336 bit ^= (tmp >> 6) ^ tmp;
337 tmp = ha->addr[3];
338 bit ^= (tmp >> 2) ^ (tmp << 4);
339 tmp = ha->addr[4];
340 bit ^= (tmp >> 4) ^ (tmp << 2);
341 tmp = ha->addr[5];
342 bit ^= (tmp >> 6) ^ tmp;
343 bit &= 0x3f;
344 hash[bit / 32] |= 1 << (bit % 32);
345 }
346
347 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
348 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
349 }
350 }
351 }
352
cpmac_rx_one(struct cpmac_priv * priv,struct cpmac_desc * desc)353 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
354 struct cpmac_desc *desc)
355 {
356 struct sk_buff *skb, *result = NULL;
357
358 if (unlikely(netif_msg_hw(priv)))
359 cpmac_dump_desc(priv->dev, desc);
360 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
361 if (unlikely(!desc->datalen)) {
362 if (netif_msg_rx_err(priv) && net_ratelimit())
363 netdev_warn(priv->dev, "rx: spurious interrupt\n");
364
365 return NULL;
366 }
367
368 skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
369 if (likely(skb)) {
370 skb_put(desc->skb, desc->datalen);
371 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
372 skb_checksum_none_assert(desc->skb);
373 priv->dev->stats.rx_packets++;
374 priv->dev->stats.rx_bytes += desc->datalen;
375 result = desc->skb;
376 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
377 CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
378 desc->skb = skb;
379 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
380 CPMAC_SKB_SIZE,
381 DMA_FROM_DEVICE);
382 desc->hw_data = (u32)desc->data_mapping;
383 if (unlikely(netif_msg_pktdata(priv))) {
384 netdev_dbg(priv->dev, "received packet:\n");
385 cpmac_dump_skb(priv->dev, result);
386 }
387 } else {
388 if (netif_msg_rx_err(priv) && net_ratelimit())
389 netdev_warn(priv->dev,
390 "low on skbs, dropping packet\n");
391
392 priv->dev->stats.rx_dropped++;
393 }
394
395 desc->buflen = CPMAC_SKB_SIZE;
396 desc->dataflags = CPMAC_OWN;
397
398 return result;
399 }
400
cpmac_poll(struct napi_struct * napi,int budget)401 static int cpmac_poll(struct napi_struct *napi, int budget)
402 {
403 struct sk_buff *skb;
404 struct cpmac_desc *desc, *restart;
405 struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
406 int received = 0, processed = 0;
407
408 spin_lock(&priv->rx_lock);
409 if (unlikely(!priv->rx_head)) {
410 if (netif_msg_rx_err(priv) && net_ratelimit())
411 netdev_warn(priv->dev, "rx: polling, but no queue\n");
412
413 spin_unlock(&priv->rx_lock);
414 napi_complete(napi);
415 return 0;
416 }
417
418 desc = priv->rx_head;
419 restart = NULL;
420 while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
421 processed++;
422
423 if ((desc->dataflags & CPMAC_EOQ) != 0) {
424 /* The last update to eoq->hw_next didn't happen
425 * soon enough, and the receiver stopped here.
426 * Remember this descriptor so we can restart
427 * the receiver after freeing some space.
428 */
429 if (unlikely(restart)) {
430 if (netif_msg_rx_err(priv))
431 netdev_err(priv->dev, "poll found a"
432 " duplicate EOQ: %p and %p\n",
433 restart, desc);
434 goto fatal_error;
435 }
436
437 restart = desc->next;
438 }
439
440 skb = cpmac_rx_one(priv, desc);
441 if (likely(skb)) {
442 netif_receive_skb(skb);
443 received++;
444 }
445 desc = desc->next;
446 }
447
448 if (desc != priv->rx_head) {
449 /* We freed some buffers, but not the whole ring,
450 * add what we did free to the rx list
451 */
452 desc->prev->hw_next = (u32)0;
453 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
454 }
455
456 /* Optimization: If we did not actually process an EOQ (perhaps because
457 * of quota limits), check to see if the tail of the queue has EOQ set.
458 * We should immediately restart in that case so that the receiver can
459 * restart and run in parallel with more packet processing.
460 * This lets us handle slightly larger bursts before running
461 * out of ring space (assuming dev->weight < ring_size)
462 */
463
464 if (!restart &&
465 (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
466 == CPMAC_EOQ &&
467 (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
468 /* reset EOQ so the poll loop (above) doesn't try to
469 * restart this when it eventually gets to this descriptor.
470 */
471 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
472 restart = priv->rx_head;
473 }
474
475 if (restart) {
476 priv->dev->stats.rx_errors++;
477 priv->dev->stats.rx_fifo_errors++;
478 if (netif_msg_rx_err(priv) && net_ratelimit())
479 netdev_warn(priv->dev, "rx dma ring overrun\n");
480
481 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
482 if (netif_msg_drv(priv))
483 netdev_err(priv->dev, "cpmac_poll is trying "
484 "to restart rx from a descriptor "
485 "that's not free: %p\n", restart);
486 goto fatal_error;
487 }
488
489 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
490 }
491
492 priv->rx_head = desc;
493 spin_unlock(&priv->rx_lock);
494 if (unlikely(netif_msg_rx_status(priv)))
495 netdev_dbg(priv->dev, "poll processed %d packets\n", received);
496
497 if (processed == 0) {
498 /* we ran out of packets to read,
499 * revert to interrupt-driven mode
500 */
501 napi_complete(napi);
502 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
503 return 0;
504 }
505
506 return 1;
507
508 fatal_error:
509 /* Something went horribly wrong.
510 * Reset hardware to try to recover rather than wedging.
511 */
512 if (netif_msg_drv(priv)) {
513 netdev_err(priv->dev, "cpmac_poll is confused. "
514 "Resetting hardware\n");
515 cpmac_dump_all_desc(priv->dev);
516 netdev_dbg(priv->dev, "RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
517 cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
518 cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
519 }
520
521 spin_unlock(&priv->rx_lock);
522 napi_complete(napi);
523 netif_tx_stop_all_queues(priv->dev);
524 napi_disable(&priv->napi);
525
526 atomic_inc(&priv->reset_pending);
527 cpmac_hw_stop(priv->dev);
528 if (!schedule_work(&priv->reset_work))
529 atomic_dec(&priv->reset_pending);
530
531 return 0;
532
533 }
534
cpmac_start_xmit(struct sk_buff * skb,struct net_device * dev)535 static netdev_tx_t cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
536 {
537 int queue;
538 unsigned int len;
539 struct cpmac_desc *desc;
540 struct cpmac_priv *priv = netdev_priv(dev);
541
542 if (unlikely(atomic_read(&priv->reset_pending)))
543 return NETDEV_TX_BUSY;
544
545 if (unlikely(skb_padto(skb, ETH_ZLEN)))
546 return NETDEV_TX_OK;
547
548 len = max_t(unsigned int, skb->len, ETH_ZLEN);
549 queue = skb_get_queue_mapping(skb);
550 netif_stop_subqueue(dev, queue);
551
552 desc = &priv->desc_ring[queue];
553 if (unlikely(desc->dataflags & CPMAC_OWN)) {
554 if (netif_msg_tx_err(priv) && net_ratelimit())
555 netdev_warn(dev, "tx dma ring full\n");
556
557 return NETDEV_TX_BUSY;
558 }
559
560 spin_lock(&priv->lock);
561 spin_unlock(&priv->lock);
562 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
563 desc->skb = skb;
564 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
565 DMA_TO_DEVICE);
566 desc->hw_data = (u32)desc->data_mapping;
567 desc->datalen = len;
568 desc->buflen = len;
569 if (unlikely(netif_msg_tx_queued(priv)))
570 netdev_dbg(dev, "sending 0x%p, len=%d\n", skb, skb->len);
571 if (unlikely(netif_msg_hw(priv)))
572 cpmac_dump_desc(dev, desc);
573 if (unlikely(netif_msg_pktdata(priv)))
574 cpmac_dump_skb(dev, skb);
575 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
576
577 return NETDEV_TX_OK;
578 }
579
cpmac_end_xmit(struct net_device * dev,int queue)580 static void cpmac_end_xmit(struct net_device *dev, int queue)
581 {
582 struct cpmac_desc *desc;
583 struct cpmac_priv *priv = netdev_priv(dev);
584
585 desc = &priv->desc_ring[queue];
586 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
587 if (likely(desc->skb)) {
588 spin_lock(&priv->lock);
589 dev->stats.tx_packets++;
590 dev->stats.tx_bytes += desc->skb->len;
591 spin_unlock(&priv->lock);
592 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
593 DMA_TO_DEVICE);
594
595 if (unlikely(netif_msg_tx_done(priv)))
596 netdev_dbg(dev, "sent 0x%p, len=%d\n",
597 desc->skb, desc->skb->len);
598
599 dev_consume_skb_irq(desc->skb);
600 desc->skb = NULL;
601 if (__netif_subqueue_stopped(dev, queue))
602 netif_wake_subqueue(dev, queue);
603 } else {
604 if (netif_msg_tx_err(priv) && net_ratelimit())
605 netdev_warn(dev, "end_xmit: spurious interrupt\n");
606 if (__netif_subqueue_stopped(dev, queue))
607 netif_wake_subqueue(dev, queue);
608 }
609 }
610
cpmac_hw_stop(struct net_device * dev)611 static void cpmac_hw_stop(struct net_device *dev)
612 {
613 int i;
614 struct cpmac_priv *priv = netdev_priv(dev);
615 struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
616
617 ar7_device_reset(pdata->reset_bit);
618 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
619 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
620 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
621 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
622 for (i = 0; i < 8; i++) {
623 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
624 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
625 }
626 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
627 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
628 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
629 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
630 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
631 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
632 }
633
cpmac_hw_start(struct net_device * dev)634 static void cpmac_hw_start(struct net_device *dev)
635 {
636 int i;
637 struct cpmac_priv *priv = netdev_priv(dev);
638 struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
639
640 ar7_device_reset(pdata->reset_bit);
641 for (i = 0; i < 8; i++) {
642 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
643 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
644 }
645 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
646
647 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
648 MBP_RXMCAST);
649 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
650 for (i = 0; i < 8; i++)
651 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
652 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
653 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
654 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
655 (dev->dev_addr[3] << 24));
656 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
657 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
658 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
659 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
660 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
661 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
662 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
663 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
664 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
665
666 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
667 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
668 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
669 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
670 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
671 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
672 MAC_FDX);
673 }
674
cpmac_clear_rx(struct net_device * dev)675 static void cpmac_clear_rx(struct net_device *dev)
676 {
677 struct cpmac_priv *priv = netdev_priv(dev);
678 struct cpmac_desc *desc;
679 int i;
680
681 if (unlikely(!priv->rx_head))
682 return;
683 desc = priv->rx_head;
684 for (i = 0; i < priv->ring_size; i++) {
685 if ((desc->dataflags & CPMAC_OWN) == 0) {
686 if (netif_msg_rx_err(priv) && net_ratelimit())
687 netdev_warn(dev, "packet dropped\n");
688 if (unlikely(netif_msg_hw(priv)))
689 cpmac_dump_desc(dev, desc);
690 desc->dataflags = CPMAC_OWN;
691 dev->stats.rx_dropped++;
692 }
693 desc->hw_next = desc->next->mapping;
694 desc = desc->next;
695 }
696 priv->rx_head->prev->hw_next = 0;
697 }
698
cpmac_clear_tx(struct net_device * dev)699 static void cpmac_clear_tx(struct net_device *dev)
700 {
701 struct cpmac_priv *priv = netdev_priv(dev);
702 int i;
703
704 if (unlikely(!priv->desc_ring))
705 return;
706 for (i = 0; i < CPMAC_QUEUES; i++) {
707 priv->desc_ring[i].dataflags = 0;
708 if (priv->desc_ring[i].skb) {
709 dev_kfree_skb_any(priv->desc_ring[i].skb);
710 priv->desc_ring[i].skb = NULL;
711 }
712 }
713 }
714
cpmac_hw_error(struct work_struct * work)715 static void cpmac_hw_error(struct work_struct *work)
716 {
717 struct cpmac_priv *priv =
718 container_of(work, struct cpmac_priv, reset_work);
719
720 spin_lock(&priv->rx_lock);
721 cpmac_clear_rx(priv->dev);
722 spin_unlock(&priv->rx_lock);
723 cpmac_clear_tx(priv->dev);
724 cpmac_hw_start(priv->dev);
725 barrier();
726 atomic_dec(&priv->reset_pending);
727
728 netif_tx_wake_all_queues(priv->dev);
729 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
730 }
731
cpmac_check_status(struct net_device * dev)732 static void cpmac_check_status(struct net_device *dev)
733 {
734 struct cpmac_priv *priv = netdev_priv(dev);
735
736 u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
737 int rx_channel = (macstatus >> 8) & 7;
738 int rx_code = (macstatus >> 12) & 15;
739 int tx_channel = (macstatus >> 16) & 7;
740 int tx_code = (macstatus >> 20) & 15;
741
742 if (rx_code || tx_code) {
743 if (netif_msg_drv(priv) && net_ratelimit()) {
744 /* Can't find any documentation on what these
745 * error codes actually are. So just log them and hope..
746 */
747 if (rx_code)
748 netdev_warn(dev, "host error %d on rx "
749 "channel %d (macstatus %08x), resetting\n",
750 rx_code, rx_channel, macstatus);
751 if (tx_code)
752 netdev_warn(dev, "host error %d on tx "
753 "channel %d (macstatus %08x), resetting\n",
754 tx_code, tx_channel, macstatus);
755 }
756
757 netif_tx_stop_all_queues(dev);
758 cpmac_hw_stop(dev);
759 if (schedule_work(&priv->reset_work))
760 atomic_inc(&priv->reset_pending);
761 if (unlikely(netif_msg_hw(priv)))
762 cpmac_dump_regs(dev);
763 }
764 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
765 }
766
cpmac_irq(int irq,void * dev_id)767 static irqreturn_t cpmac_irq(int irq, void *dev_id)
768 {
769 struct net_device *dev = dev_id;
770 struct cpmac_priv *priv;
771 int queue;
772 u32 status;
773
774 priv = netdev_priv(dev);
775
776 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
777
778 if (unlikely(netif_msg_intr(priv)))
779 netdev_dbg(dev, "interrupt status: 0x%08x\n", status);
780
781 if (status & MAC_INT_TX)
782 cpmac_end_xmit(dev, (status & 7));
783
784 if (status & MAC_INT_RX) {
785 queue = (status >> 8) & 7;
786 if (napi_schedule_prep(&priv->napi)) {
787 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
788 __napi_schedule(&priv->napi);
789 }
790 }
791
792 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
793
794 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
795 cpmac_check_status(dev);
796
797 return IRQ_HANDLED;
798 }
799
cpmac_tx_timeout(struct net_device * dev,unsigned int txqueue)800 static void cpmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
801 {
802 struct cpmac_priv *priv = netdev_priv(dev);
803
804 spin_lock(&priv->lock);
805 dev->stats.tx_errors++;
806 spin_unlock(&priv->lock);
807 if (netif_msg_tx_err(priv) && net_ratelimit())
808 netdev_warn(dev, "transmit timeout\n");
809
810 atomic_inc(&priv->reset_pending);
811 barrier();
812 cpmac_clear_tx(dev);
813 barrier();
814 atomic_dec(&priv->reset_pending);
815
816 netif_tx_wake_all_queues(priv->dev);
817 }
818
cpmac_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)819 static void cpmac_get_ringparam(struct net_device *dev,
820 struct ethtool_ringparam *ring,
821 struct kernel_ethtool_ringparam *kernel_ring,
822 struct netlink_ext_ack *extack)
823 {
824 struct cpmac_priv *priv = netdev_priv(dev);
825
826 ring->rx_max_pending = 1024;
827 ring->rx_mini_max_pending = 1;
828 ring->rx_jumbo_max_pending = 1;
829 ring->tx_max_pending = 1;
830
831 ring->rx_pending = priv->ring_size;
832 ring->rx_mini_pending = 1;
833 ring->rx_jumbo_pending = 1;
834 ring->tx_pending = 1;
835 }
836
cpmac_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)837 static int cpmac_set_ringparam(struct net_device *dev,
838 struct ethtool_ringparam *ring,
839 struct kernel_ethtool_ringparam *kernel_ring,
840 struct netlink_ext_ack *extack)
841 {
842 struct cpmac_priv *priv = netdev_priv(dev);
843
844 if (netif_running(dev))
845 return -EBUSY;
846 priv->ring_size = ring->rx_pending;
847
848 return 0;
849 }
850
cpmac_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)851 static void cpmac_get_drvinfo(struct net_device *dev,
852 struct ethtool_drvinfo *info)
853 {
854 strscpy(info->driver, "cpmac", sizeof(info->driver));
855 strscpy(info->version, CPMAC_VERSION, sizeof(info->version));
856 snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac");
857 }
858
859 static const struct ethtool_ops cpmac_ethtool_ops = {
860 .get_drvinfo = cpmac_get_drvinfo,
861 .get_link = ethtool_op_get_link,
862 .get_ringparam = cpmac_get_ringparam,
863 .set_ringparam = cpmac_set_ringparam,
864 .get_link_ksettings = phy_ethtool_get_link_ksettings,
865 .set_link_ksettings = phy_ethtool_set_link_ksettings,
866 };
867
cpmac_adjust_link(struct net_device * dev)868 static void cpmac_adjust_link(struct net_device *dev)
869 {
870 struct cpmac_priv *priv = netdev_priv(dev);
871 int new_state = 0;
872
873 spin_lock(&priv->lock);
874 if (dev->phydev->link) {
875 netif_tx_start_all_queues(dev);
876 if (dev->phydev->duplex != priv->oldduplex) {
877 new_state = 1;
878 priv->oldduplex = dev->phydev->duplex;
879 }
880
881 if (dev->phydev->speed != priv->oldspeed) {
882 new_state = 1;
883 priv->oldspeed = dev->phydev->speed;
884 }
885
886 if (!priv->oldlink) {
887 new_state = 1;
888 priv->oldlink = 1;
889 }
890 } else if (priv->oldlink) {
891 new_state = 1;
892 priv->oldlink = 0;
893 priv->oldspeed = 0;
894 priv->oldduplex = -1;
895 }
896
897 if (new_state && netif_msg_link(priv) && net_ratelimit())
898 phy_print_status(dev->phydev);
899
900 spin_unlock(&priv->lock);
901 }
902
cpmac_open(struct net_device * dev)903 static int cpmac_open(struct net_device *dev)
904 {
905 int i, size, res;
906 struct cpmac_priv *priv = netdev_priv(dev);
907 struct resource *mem;
908 struct cpmac_desc *desc;
909 struct sk_buff *skb;
910
911 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
912 if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
913 if (netif_msg_drv(priv))
914 netdev_err(dev, "failed to request registers\n");
915
916 res = -ENXIO;
917 goto fail_reserve;
918 }
919
920 priv->regs = ioremap(mem->start, resource_size(mem));
921 if (!priv->regs) {
922 if (netif_msg_drv(priv))
923 netdev_err(dev, "failed to remap registers\n");
924
925 res = -ENXIO;
926 goto fail_remap;
927 }
928
929 size = priv->ring_size + CPMAC_QUEUES;
930 priv->desc_ring = dma_alloc_coherent(&dev->dev,
931 sizeof(struct cpmac_desc) * size,
932 &priv->dma_ring,
933 GFP_KERNEL);
934 if (!priv->desc_ring) {
935 res = -ENOMEM;
936 goto fail_alloc;
937 }
938
939 for (i = 0; i < size; i++)
940 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
941
942 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
943 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
944 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
945 if (unlikely(!skb)) {
946 res = -ENOMEM;
947 goto fail_desc;
948 }
949 desc->skb = skb;
950 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
951 CPMAC_SKB_SIZE,
952 DMA_FROM_DEVICE);
953 desc->hw_data = (u32)desc->data_mapping;
954 desc->buflen = CPMAC_SKB_SIZE;
955 desc->dataflags = CPMAC_OWN;
956 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
957 desc->next->prev = desc;
958 desc->hw_next = (u32)desc->next->mapping;
959 }
960
961 priv->rx_head->prev->hw_next = (u32)0;
962
963 res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev);
964 if (res) {
965 if (netif_msg_drv(priv))
966 netdev_err(dev, "failed to obtain irq\n");
967
968 goto fail_irq;
969 }
970
971 atomic_set(&priv->reset_pending, 0);
972 INIT_WORK(&priv->reset_work, cpmac_hw_error);
973 cpmac_hw_start(dev);
974
975 napi_enable(&priv->napi);
976 phy_start(dev->phydev);
977
978 return 0;
979
980 fail_irq:
981 fail_desc:
982 for (i = 0; i < priv->ring_size; i++) {
983 if (priv->rx_head[i].skb) {
984 dma_unmap_single(&dev->dev,
985 priv->rx_head[i].data_mapping,
986 CPMAC_SKB_SIZE,
987 DMA_FROM_DEVICE);
988 kfree_skb(priv->rx_head[i].skb);
989 }
990 }
991 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) * size,
992 priv->desc_ring, priv->dma_ring);
993
994 fail_alloc:
995 iounmap(priv->regs);
996
997 fail_remap:
998 release_mem_region(mem->start, resource_size(mem));
999
1000 fail_reserve:
1001 return res;
1002 }
1003
cpmac_stop(struct net_device * dev)1004 static int cpmac_stop(struct net_device *dev)
1005 {
1006 int i;
1007 struct cpmac_priv *priv = netdev_priv(dev);
1008 struct resource *mem;
1009
1010 netif_tx_stop_all_queues(dev);
1011
1012 cancel_work_sync(&priv->reset_work);
1013 napi_disable(&priv->napi);
1014 phy_stop(dev->phydev);
1015
1016 cpmac_hw_stop(dev);
1017
1018 for (i = 0; i < 8; i++)
1019 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1020 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1021 cpmac_write(priv->regs, CPMAC_MBP, 0);
1022
1023 free_irq(dev->irq, dev);
1024 iounmap(priv->regs);
1025 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1026 release_mem_region(mem->start, resource_size(mem));
1027 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1028 for (i = 0; i < priv->ring_size; i++) {
1029 if (priv->rx_head[i].skb) {
1030 dma_unmap_single(&dev->dev,
1031 priv->rx_head[i].data_mapping,
1032 CPMAC_SKB_SIZE,
1033 DMA_FROM_DEVICE);
1034 kfree_skb(priv->rx_head[i].skb);
1035 }
1036 }
1037
1038 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1039 (CPMAC_QUEUES + priv->ring_size),
1040 priv->desc_ring, priv->dma_ring);
1041
1042 return 0;
1043 }
1044
1045 static const struct net_device_ops cpmac_netdev_ops = {
1046 .ndo_open = cpmac_open,
1047 .ndo_stop = cpmac_stop,
1048 .ndo_start_xmit = cpmac_start_xmit,
1049 .ndo_tx_timeout = cpmac_tx_timeout,
1050 .ndo_set_rx_mode = cpmac_set_multicast_list,
1051 .ndo_eth_ioctl = phy_do_ioctl_running,
1052 .ndo_validate_addr = eth_validate_addr,
1053 .ndo_set_mac_address = eth_mac_addr,
1054 };
1055
1056 static int external_switch;
1057
cpmac_probe(struct platform_device * pdev)1058 static int cpmac_probe(struct platform_device *pdev)
1059 {
1060 int rc, phy_id;
1061 char mdio_bus_id[MII_BUS_ID_SIZE];
1062 struct resource *mem;
1063 struct cpmac_priv *priv;
1064 struct net_device *dev;
1065 struct plat_cpmac_data *pdata;
1066 struct phy_device *phydev = NULL;
1067
1068 pdata = dev_get_platdata(&pdev->dev);
1069
1070 if (external_switch || dumb_switch) {
1071 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1072 phy_id = pdev->id;
1073 } else {
1074 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1075 if (!(pdata->phy_mask & (1 << phy_id)))
1076 continue;
1077 if (!mdiobus_get_phy(cpmac_mii, phy_id))
1078 continue;
1079 strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1080 break;
1081 }
1082 }
1083
1084 if (phy_id == PHY_MAX_ADDR) {
1085 dev_err(&pdev->dev, "no PHY present, falling back "
1086 "to switch on MDIO bus 0\n");
1087 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1088 phy_id = pdev->id;
1089 }
1090 mdio_bus_id[sizeof(mdio_bus_id) - 1] = '\0';
1091
1092 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1093 if (!dev)
1094 return -ENOMEM;
1095
1096 SET_NETDEV_DEV(dev, &pdev->dev);
1097 platform_set_drvdata(pdev, dev);
1098 priv = netdev_priv(dev);
1099
1100 priv->pdev = pdev;
1101 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1102 if (!mem) {
1103 rc = -ENODEV;
1104 goto fail;
1105 }
1106
1107 dev->irq = platform_get_irq_byname(pdev, "irq");
1108
1109 dev->netdev_ops = &cpmac_netdev_ops;
1110 dev->ethtool_ops = &cpmac_ethtool_ops;
1111
1112 netif_napi_add(dev, &priv->napi, cpmac_poll);
1113
1114 spin_lock_init(&priv->lock);
1115 spin_lock_init(&priv->rx_lock);
1116 priv->dev = dev;
1117 priv->ring_size = 64;
1118 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1119 eth_hw_addr_set(dev, pdata->dev_addr);
1120
1121 snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
1122 mdio_bus_id, phy_id);
1123
1124 phydev = phy_connect(dev, priv->phy_name, cpmac_adjust_link,
1125 PHY_INTERFACE_MODE_MII);
1126
1127 if (IS_ERR(phydev)) {
1128 if (netif_msg_drv(priv))
1129 dev_err(&pdev->dev, "Could not attach to PHY\n");
1130
1131 rc = PTR_ERR(phydev);
1132 goto fail;
1133 }
1134
1135 rc = register_netdev(dev);
1136 if (rc) {
1137 dev_err(&pdev->dev, "Could not register net device\n");
1138 goto fail;
1139 }
1140
1141 if (netif_msg_probe(priv)) {
1142 dev_info(&pdev->dev, "regs: %p, irq: %d, phy: %s, "
1143 "mac: %pM\n", (void *)mem->start, dev->irq,
1144 priv->phy_name, dev->dev_addr);
1145 }
1146
1147 return 0;
1148
1149 fail:
1150 free_netdev(dev);
1151 return rc;
1152 }
1153
cpmac_remove(struct platform_device * pdev)1154 static int cpmac_remove(struct platform_device *pdev)
1155 {
1156 struct net_device *dev = platform_get_drvdata(pdev);
1157
1158 unregister_netdev(dev);
1159 free_netdev(dev);
1160
1161 return 0;
1162 }
1163
1164 static struct platform_driver cpmac_driver = {
1165 .driver = {
1166 .name = "cpmac",
1167 },
1168 .probe = cpmac_probe,
1169 .remove = cpmac_remove,
1170 };
1171
cpmac_init(void)1172 int __init cpmac_init(void)
1173 {
1174 u32 mask;
1175 int i, res;
1176
1177 cpmac_mii = mdiobus_alloc();
1178 if (cpmac_mii == NULL)
1179 return -ENOMEM;
1180
1181 cpmac_mii->name = "cpmac-mii";
1182 cpmac_mii->read = cpmac_mdio_read;
1183 cpmac_mii->write = cpmac_mdio_write;
1184 cpmac_mii->reset = cpmac_mdio_reset;
1185
1186 cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1187
1188 if (!cpmac_mii->priv) {
1189 pr_err("Can't ioremap mdio registers\n");
1190 res = -ENXIO;
1191 goto fail_alloc;
1192 }
1193
1194 /* FIXME: unhardcode gpio&reset bits */
1195 ar7_gpio_disable(26);
1196 ar7_gpio_disable(27);
1197 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1198 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1199 ar7_device_reset(AR7_RESET_BIT_EPHY);
1200
1201 cpmac_mii->reset(cpmac_mii);
1202
1203 for (i = 0; i < 300; i++) {
1204 mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE);
1205 if (mask)
1206 break;
1207 else
1208 msleep(10);
1209 }
1210
1211 mask &= 0x7fffffff;
1212 if (mask & (mask - 1)) {
1213 external_switch = 1;
1214 mask = 0;
1215 }
1216
1217 cpmac_mii->phy_mask = ~(mask | 0x80000000);
1218 snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
1219
1220 res = mdiobus_register(cpmac_mii);
1221 if (res)
1222 goto fail_mii;
1223
1224 res = platform_driver_register(&cpmac_driver);
1225 if (res)
1226 goto fail_cpmac;
1227
1228 return 0;
1229
1230 fail_cpmac:
1231 mdiobus_unregister(cpmac_mii);
1232
1233 fail_mii:
1234 iounmap(cpmac_mii->priv);
1235
1236 fail_alloc:
1237 mdiobus_free(cpmac_mii);
1238
1239 return res;
1240 }
1241
cpmac_exit(void)1242 void __exit cpmac_exit(void)
1243 {
1244 platform_driver_unregister(&cpmac_driver);
1245 mdiobus_unregister(cpmac_mii);
1246 iounmap(cpmac_mii->priv);
1247 mdiobus_free(cpmac_mii);
1248 }
1249
1250 module_init(cpmac_init);
1251 module_exit(cpmac_exit);
1252
