Searched refs:CPM (Results 1 – 25 of 25) sorted by relevance
1 PPC4xx Clock Power Management (CPM) node9 - er-offset : All 4xx SoCs with a CPM controller have10 one of two different order for the CPM11 registers. Some have the CPM registers18 in CPM will be set to turn off unused22 in CPM will be set to turn off unused23 devices. This is usually just CPM[CPU].26 in CPM will be set on standby and30 in CPM will be set on suspend (mem) and
14 coprocessors on Freescale embedded CPUs (akin to CPM in older chips).37 tristate "CPM TSA support"39 depends on CPM1 || (CPM && COMPILE_TEST)41 Freescale CPM Time Slot Assigner (TSA)48 tristate "CPM QMC support"50 depends on CPM1 || (FSL_SOC && CPM && COMPILE_TEST)53 Freescale CPM QUICC Multichannel Controller
7 * Root CPM node22 * Properties common to multiple CPM/QE devices25 to specify the device on which a CPM command operates.38 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.47 CPM-side offsets with pointer subtraction. It is recommended that
5 in with the CPM binding later in this document.17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
37 …| CPM (core) | 0 | 0 | Snoop-Logic | CPM # …39 …| CPM (core) | 0 | 2 | Armv8 Core 1 | CPM # …
24 QE and two options for CPM.
18 CPM UART driver, the port-number is required for the QE UART driver.
3 The I2C controller is expressed as a bus under the CPM node.
4 select CPM94 menu "MPC8xx CPM Options"
242 bool "Early serial debugging for Freescale CPM-based serial ports"246 using a CPM-based serial port. This assumes that the bootwrapper247 has run, and set up the CPM in a particular way.352 hex "CPM UART early debug transmit descriptor address"
1120 PPC4xx Clock Power Management (CPM) support (suspend/resume).
65 /* CON15,16 - CPM lane 4 */245 /* CPM Lane 5 - U29 */
146 * SPI on CPM and NAND have common pins on this board. We can
474 * this controller is only usable on the CPM
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
105 CPM, enumerator635 .version = CPM,
338 bool "Xilinx Versal CPM PCI controller"343 Xilinx Versal CPM host bridge.
255 select CPM276 config CPM config
764 * Since our pcie doesn't support ClockPM(CPM), we want766 * de-assert it along and make ClockPM(CPM) work.
316 tristate "Freescale QE/CPM USB Device Controller"317 depends on FSL_SOC && (QUICC_ENGINE || CPM)
764 tristate "CPM SCC/SMC serial port support"772 bool "Support for console on CPM SCC/SMC serial port"776 Say Y here if you wish to use a SCC or SMC CPM UART as the system
598 MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
2692 46 = /dev/ttyCPM0 PPC CPM (SCC or SMC) - port 02694 51 = /dev/ttyCPM5 PPC CPM (SCC or SMC) - port 5
2733 A passthrough module (OPM or CPM, optical or copper,
8278 FREESCALE I2C CPM DRIVER16464 PCI DRIVER FOR XILINX VERSAL CPM
