Searched refs:CPG_PL5_SDIV_DIV_DSI_A_WEN (Results 1 – 2 of 2) sorted by relevance
40 #define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) macro
372 writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN | in rzg2l_cpg_dsi_div_set_rate()
