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Searched refs:CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h1495 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
Dgfx_8_0_sh_mask.h1929 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
Dgfx_8_1_sh_mask.h2451 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11888 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_9_2_1_sh_mask.h13096 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_9_4_3_sh_mask.h15099 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_9_1_sh_mask.h13318 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_9_4_2_sh_mask.h3294 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_11_0_0_sh_mask.h16329 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_10_1_0_sh_mask.h18872 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_11_0_3_sh_mask.h18572 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro
Dgc_10_3_0_sh_mask.h17220 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK … macro