Searched refs:COMPOSITE (Results 1 – 17 of 17) sorted by relevance
705 COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,708 COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,711 COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,714 COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,717 COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,720 COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,723 COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL,726 COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,732 COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,735 COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL,[all …]
271 COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,309 COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,318 COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,330 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,349 COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,363 COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,370 COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,380 COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,393 COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,406 COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,[all …]
330 COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,340 COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,350 COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,360 COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,370 COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,380 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,383 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,386 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,389 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,393 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,[all …]
425 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,444 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,448 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,452 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,456 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,460 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,464 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,548 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,567 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,583 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,[all …]
226 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,281 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,287 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,293 COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,297 COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,302 COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,308 COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,317 COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,321 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,325 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,[all …]
219 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,224 COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0,237 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0,242 COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0,246 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,249 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,285 COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0,288 COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,297 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,346 COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,[all …]
384 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,390 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,393 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,406 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,415 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,419 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,422 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,431 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,442 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,448 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,[all …]
235 COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,251 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0,256 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0,262 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0,267 COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0,270 COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,273 COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0,319 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,323 COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,327 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,[all …]
294 COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,320 COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,327 COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,333 COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,419 COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,424 COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,429 COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,445 COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,459 COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,470 COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,[all …]
320 COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,356 COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,367 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,379 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,388 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,398 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,416 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,419 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,430 COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,433 COMPOSITE(0, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,[all …]
360 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,414 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,417 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,431 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,434 COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,438 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,441 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,445 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,448 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,455 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,[all …]
485 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,528 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,550 COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,580 COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,617 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0,630 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0,643 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0,656 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0,669 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0,682 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0,[all …]
211 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,263 COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,269 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,273 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,276 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,279 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,295 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,308 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,321 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,332 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,[all …]
287 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,292 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,300 COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,314 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,317 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,354 COMPOSITE(0, "mac_src", mux_mac_p, 0,362 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,575 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,579 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,584 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,[all …]
550 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ macro
1364 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ macro1386 COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\1762 COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,1779 COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,1784 COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,1789 COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,1794 COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,1799 COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,1804 COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,1809 COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,[all …]
23 .. _MEDIA-ENT-F-CONN-COMPOSITE:
