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Searched refs:CLK_TOP_MSDC50_3_HCLK_SEL (Results 1 – 2 of 2) sorted by relevance

/Linux-v6.6/include/dt-bindings/clock/
Dmt2712-clk.h165 #define CLK_TOP_MSDC50_3_HCLK_SEL 134 macro
/Linux-v6.6/drivers/clk/mediatek/
Dclk-mt2712.c702 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", msdc50_0_h_parents,