Searched refs:CLK_TOP_APLL2_DIV4 (Results 1 – 4 of 4) sorted by relevance
| /Linux-v6.6/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 136 #define CLK_TOP_APLL2_DIV4 125 macro
|
| D | mt8173-clk.h | 141 #define CLK_TOP_APLL2_DIV4 131 macro
|
| /Linux-v6.6/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 522 DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
|
| D | clk-mt8173-topckgen.c | 617 DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
|
