Searched refs:CLK_FIN_PLL (Results 1 – 18 of 18) sorted by relevance
| /Linux-v6.6/include/dt-bindings/clock/ |
| D | exynos5410.h | 13 #define CLK_FIN_PLL 1 macro
|
| D | exynos5250.h | 13 #define CLK_FIN_PLL 1 macro
|
| D | exynos4.h | 15 #define CLK_FIN_PLL 3 macro
|
| D | exynos5420.h | 13 #define CLK_FIN_PLL 1 macro
|
| D | exynos3250.h | 26 #define CLK_FIN_PLL 2 macro
|
| /Linux-v6.6/arch/arm/boot/dts/samsung/ |
| D | exynos3250.dtsi | 352 clocks = <&cmu CLK_FIN_PLL>;
402 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
403 <&cmu CLK_FIN_PLL>;
455 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
|
| D | exynos5250.dtsi | 237 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
247 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
292 clocks = <&clock CLK_FIN_PLL>;
664 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
695 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
|
| D | exynos5420.dtsi | 295 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
924 clocks = <&clock CLK_FIN_PLL>;
1288 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
| D | exynos4210.dtsi | 286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
| D | exynos4x12.dtsi | 299 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
| D | exynos5250-snow-common.dtsi | 672 assigned-clock-parents = <&clock CLK_FIN_PLL>;
|
| D | exynos5420-peach-pit.dts | 946 assigned-clock-parents = <&clock CLK_FIN_PLL>;
|
| D | exynos4.dtsi | 70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
|
| D | exynos5800-peach-pi.dts | 928 assigned-clock-parents = <&clock CLK_FIN_PLL>;
|
| /Linux-v6.6/drivers/clk/samsung/ |
| D | clk-exynos5250.c | 228 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
812 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init()
|
| D | clk-exynos4.c | 1058 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll()
1294 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
1308 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
|
| D | clk-exynos5420.c | 448 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
1600 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5x_clk_init()
|
| D | clk-exynos3250.c | 239 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
|
