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Searched refs:CLKID_MPLL1_DIV (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.6/include/dt-bindings/clock/
Daxg-clkc.h77 #define CLKID_MPLL1_DIV 66 macro
Dgxbb-clkc.h151 #define CLKID_MPLL1_DIV 143 macro
Dmeson8b-clkc.h104 #define CLKID_MPLL1_DIV 97 macro
Dg12a-clkc.h81 #define CLKID_MPLL1_DIV 70 macro
/Linux-v6.6/drivers/clk/meson/
Dmeson8b.c2873 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3077 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
3292 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
Dgxbb.c2876 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
3083 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
Dg12a.c4321 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4546 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4806 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
Daxg.c1962 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,