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Searched refs:CLKID_MPLL0_DIV (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.6/include/dt-bindings/clock/
Daxg-clkc.h76 #define CLKID_MPLL0_DIV 65 macro
Dgxbb-clkc.h150 #define CLKID_MPLL0_DIV 142 macro
Dmeson8b-clkc.h103 #define CLKID_MPLL0_DIV 96 macro
Dg12a-clkc.h80 #define CLKID_MPLL0_DIV 69 macro
/Linux-v6.6/drivers/clk/meson/
Dmeson8b.c2872 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3076 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3291 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
Dgxbb.c2875 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
3082 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
Dg12a.c4320 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4545 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4805 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
Daxg.c1961 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,