1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ROHM Colour Sensor driver for
4 * - BU27008 RGBC sensor
5 * - BU27010 RGBC + Flickering sensor
6 *
7 * Copyright (c) 2023, ROHM Semiconductor.
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bitops.h>
12 #include <linux/device.h>
13 #include <linux/i2c.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/units.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/iio-gts-helper.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26
27 /*
28 * A word about register address and mask definitions.
29 *
30 * At a quick glance to the data-sheet register tables, the BU27010 has all the
31 * registers that the BU27008 has. On top of that the BU27010 adds couple of new
32 * ones.
33 *
34 * So, all definitions BU27008_REG_* are there also for BU27010 but none of the
35 * BU27010_REG_* are present on BU27008. This makes sense as BU27010 just adds
36 * some features (Flicker FIFO, more power control) on top of the BU27008.
37 *
38 * Unfortunately, some of the wheel has been re-invented. Even though the names
39 * of the registers have stayed the same, pretty much all of the functionality
40 * provided by the registers has changed place. Contents of all MODE_CONTROL
41 * registers on BU27008 and BU27010 are different.
42 *
43 * Chip-specific mapping from register addresses/bits to functionality is done
44 * in bu27_chip_data structures.
45 */
46 #define BU27008_REG_SYSTEM_CONTROL 0x40
47 #define BU27008_MASK_SW_RESET BIT(7)
48 #define BU27008_MASK_PART_ID GENMASK(5, 0)
49 #define BU27008_ID 0x1a
50 #define BU27008_REG_MODE_CONTROL1 0x41
51 #define BU27008_MASK_MEAS_MODE GENMASK(2, 0)
52 #define BU27008_MASK_CHAN_SEL GENMASK(3, 2)
53
54 #define BU27008_REG_MODE_CONTROL2 0x42
55 #define BU27008_MASK_RGBC_GAIN GENMASK(7, 3)
56 #define BU27008_MASK_IR_GAIN_LO GENMASK(2, 0)
57 #define BU27008_SHIFT_IR_GAIN 3
58
59 #define BU27008_REG_MODE_CONTROL3 0x43
60 #define BU27008_MASK_VALID BIT(7)
61 #define BU27008_MASK_INT_EN BIT(1)
62 #define BU27008_INT_EN BU27008_MASK_INT_EN
63 #define BU27008_INT_DIS 0
64 #define BU27008_MASK_MEAS_EN BIT(0)
65 #define BU27008_MEAS_EN BIT(0)
66 #define BU27008_MEAS_DIS 0
67
68 #define BU27008_REG_DATA0_LO 0x50
69 #define BU27008_REG_DATA1_LO 0x52
70 #define BU27008_REG_DATA2_LO 0x54
71 #define BU27008_REG_DATA3_LO 0x56
72 #define BU27008_REG_DATA3_HI 0x57
73 #define BU27008_REG_MANUFACTURER_ID 0x92
74 #define BU27008_REG_MAX BU27008_REG_MANUFACTURER_ID
75
76 /* BU27010 specific definitions */
77
78 #define BU27010_MASK_SW_RESET BIT(7)
79 #define BU27010_ID 0x1b
80 #define BU27010_REG_POWER 0x3e
81 #define BU27010_MASK_POWER BIT(0)
82
83 #define BU27010_REG_RESET 0x3f
84 #define BU27010_MASK_RESET BIT(0)
85 #define BU27010_RESET_RELEASE BU27010_MASK_RESET
86
87 #define BU27010_MASK_MEAS_EN BIT(1)
88
89 #define BU27010_MASK_CHAN_SEL GENMASK(7, 6)
90 #define BU27010_MASK_MEAS_MODE GENMASK(5, 4)
91 #define BU27010_MASK_RGBC_GAIN GENMASK(3, 0)
92
93 #define BU27010_MASK_DATA3_GAIN GENMASK(7, 6)
94 #define BU27010_MASK_DATA2_GAIN GENMASK(5, 4)
95 #define BU27010_MASK_DATA1_GAIN GENMASK(3, 2)
96 #define BU27010_MASK_DATA0_GAIN GENMASK(1, 0)
97
98 #define BU27010_MASK_FLC_MODE BIT(7)
99 #define BU27010_MASK_FLC_GAIN GENMASK(4, 0)
100
101 #define BU27010_REG_MODE_CONTROL4 0x44
102 /* If flicker is ever to be supported the IRQ must be handled as a field */
103 #define BU27010_IRQ_DIS_ALL GENMASK(1, 0)
104 #define BU27010_DRDY_EN BIT(0)
105 #define BU27010_MASK_INT_SEL GENMASK(1, 0)
106
107 #define BU27010_REG_MODE_CONTROL5 0x45
108 #define BU27010_MASK_RGB_VALID BIT(7)
109 #define BU27010_MASK_FLC_VALID BIT(6)
110 #define BU27010_MASK_WAIT_EN BIT(3)
111 #define BU27010_MASK_FIFO_EN BIT(2)
112 #define BU27010_MASK_RGB_EN BIT(1)
113 #define BU27010_MASK_FLC_EN BIT(0)
114
115 #define BU27010_REG_DATA_FLICKER_LO 0x56
116 #define BU27010_MASK_DATA_FLICKER_HI GENMASK(2, 0)
117 #define BU27010_REG_FLICKER_COUNT 0x5a
118 #define BU27010_REG_FIFO_LEVEL_LO 0x5b
119 #define BU27010_MASK_FIFO_LEVEL_HI BIT(0)
120 #define BU27010_REG_FIFO_DATA_LO 0x5d
121 #define BU27010_REG_FIFO_DATA_HI 0x5e
122 #define BU27010_MASK_FIFO_DATA_HI GENMASK(2, 0)
123 #define BU27010_REG_MANUFACTURER_ID 0x92
124 #define BU27010_REG_MAX BU27010_REG_MANUFACTURER_ID
125
126 /**
127 * enum bu27008_chan_type - BU27008 channel types
128 * @BU27008_RED: Red channel. Always via data0.
129 * @BU27008_GREEN: Green channel. Always via data1.
130 * @BU27008_BLUE: Blue channel. Via data2 (when used).
131 * @BU27008_CLEAR: Clear channel. Via data2 or data3 (when used).
132 * @BU27008_IR: IR channel. Via data3 (when used).
133 * @BU27008_NUM_CHANS: Number of channel types.
134 */
135 enum bu27008_chan_type {
136 BU27008_RED,
137 BU27008_GREEN,
138 BU27008_BLUE,
139 BU27008_CLEAR,
140 BU27008_IR,
141 BU27008_NUM_CHANS
142 };
143
144 /**
145 * enum bu27008_chan - BU27008 physical data channel
146 * @BU27008_DATA0: Always red.
147 * @BU27008_DATA1: Always green.
148 * @BU27008_DATA2: Blue or clear.
149 * @BU27008_DATA3: IR or clear.
150 * @BU27008_NUM_HW_CHANS: Number of physical channels
151 */
152 enum bu27008_chan {
153 BU27008_DATA0,
154 BU27008_DATA1,
155 BU27008_DATA2,
156 BU27008_DATA3,
157 BU27008_NUM_HW_CHANS
158 };
159
160 /* We can always measure red and green at same time */
161 #define ALWAYS_SCANNABLE (BIT(BU27008_RED) | BIT(BU27008_GREEN))
162
163 /* We use these data channel configs. Ensure scan_masks below follow them too */
164 #define BU27008_BLUE2_CLEAR3 0x0 /* buffer is R, G, B, C */
165 #define BU27008_CLEAR2_IR3 0x1 /* buffer is R, G, C, IR */
166 #define BU27008_BLUE2_IR3 0x2 /* buffer is R, G, B, IR */
167
168 static const unsigned long bu27008_scan_masks[] = {
169 /* buffer is R, G, B, C */
170 ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_CLEAR),
171 /* buffer is R, G, C, IR */
172 ALWAYS_SCANNABLE | BIT(BU27008_CLEAR) | BIT(BU27008_IR),
173 /* buffer is R, G, B, IR */
174 ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_IR),
175 0
176 };
177
178 /*
179 * Available scales with gain 1x - 1024x, timings 55, 100, 200, 400 mS
180 * Time impacts to gain: 1x, 2x, 4x, 8x.
181 *
182 * => Max total gain is HWGAIN * gain by integration time (8 * 1024) = 8192
183 *
184 * Max amplification is (HWGAIN * MAX integration-time multiplier) 1024 * 8
185 * = 8192. With NANO scale we get rid of accuracy loss when we start with the
186 * scale 16.0 for HWGAIN1, INT-TIME 55 mS. This way the nano scale for MAX
187 * total gain 8192 will be 1953125
188 */
189 #define BU27008_SCALE_1X 16
190
191 /*
192 * On BU27010 available scales with gain 1x - 4096x,
193 * timings 55, 100, 200, 400 mS. Time impacts to gain: 1x, 2x, 4x, 8x.
194 *
195 * => Max total gain is HWGAIN * gain by integration time (8 * 4096)
196 *
197 * Using NANO precision for scale we must use scale 64x corresponding gain 1x
198 * to avoid precision loss.
199 */
200 #define BU27010_SCALE_1X 64
201
202 /* See the data sheet for the "Gain Setting" table */
203 #define BU27008_GSEL_1X 0x00
204 #define BU27008_GSEL_4X 0x08
205 #define BU27008_GSEL_8X 0x09
206 #define BU27008_GSEL_16X 0x0a
207 #define BU27008_GSEL_32X 0x0b
208 #define BU27008_GSEL_64X 0x0c
209 #define BU27008_GSEL_256X 0x18
210 #define BU27008_GSEL_512X 0x19
211 #define BU27008_GSEL_1024X 0x1a
212
213 static const struct iio_gain_sel_pair bu27008_gains[] = {
214 GAIN_SCALE_GAIN(1, BU27008_GSEL_1X),
215 GAIN_SCALE_GAIN(4, BU27008_GSEL_4X),
216 GAIN_SCALE_GAIN(8, BU27008_GSEL_8X),
217 GAIN_SCALE_GAIN(16, BU27008_GSEL_16X),
218 GAIN_SCALE_GAIN(32, BU27008_GSEL_32X),
219 GAIN_SCALE_GAIN(64, BU27008_GSEL_64X),
220 GAIN_SCALE_GAIN(256, BU27008_GSEL_256X),
221 GAIN_SCALE_GAIN(512, BU27008_GSEL_512X),
222 GAIN_SCALE_GAIN(1024, BU27008_GSEL_1024X),
223 };
224
225 static const struct iio_gain_sel_pair bu27008_gains_ir[] = {
226 GAIN_SCALE_GAIN(2, BU27008_GSEL_1X),
227 GAIN_SCALE_GAIN(4, BU27008_GSEL_4X),
228 GAIN_SCALE_GAIN(8, BU27008_GSEL_8X),
229 GAIN_SCALE_GAIN(16, BU27008_GSEL_16X),
230 GAIN_SCALE_GAIN(32, BU27008_GSEL_32X),
231 GAIN_SCALE_GAIN(64, BU27008_GSEL_64X),
232 GAIN_SCALE_GAIN(256, BU27008_GSEL_256X),
233 GAIN_SCALE_GAIN(512, BU27008_GSEL_512X),
234 GAIN_SCALE_GAIN(1024, BU27008_GSEL_1024X),
235 };
236
237 #define BU27010_GSEL_1X 0x00 /* 000000 */
238 #define BU27010_GSEL_4X 0x08 /* 001000 */
239 #define BU27010_GSEL_16X 0x09 /* 001001 */
240 #define BU27010_GSEL_64X 0x0e /* 001110 */
241 #define BU27010_GSEL_256X 0x1e /* 011110 */
242 #define BU27010_GSEL_1024X 0x2e /* 101110 */
243 #define BU27010_GSEL_4096X 0x3f /* 111111 */
244
245 static const struct iio_gain_sel_pair bu27010_gains[] = {
246 GAIN_SCALE_GAIN(1, BU27010_GSEL_1X),
247 GAIN_SCALE_GAIN(4, BU27010_GSEL_4X),
248 GAIN_SCALE_GAIN(16, BU27010_GSEL_16X),
249 GAIN_SCALE_GAIN(64, BU27010_GSEL_64X),
250 GAIN_SCALE_GAIN(256, BU27010_GSEL_256X),
251 GAIN_SCALE_GAIN(1024, BU27010_GSEL_1024X),
252 GAIN_SCALE_GAIN(4096, BU27010_GSEL_4096X),
253 };
254
255 static const struct iio_gain_sel_pair bu27010_gains_ir[] = {
256 GAIN_SCALE_GAIN(2, BU27010_GSEL_1X),
257 GAIN_SCALE_GAIN(4, BU27010_GSEL_4X),
258 GAIN_SCALE_GAIN(16, BU27010_GSEL_16X),
259 GAIN_SCALE_GAIN(64, BU27010_GSEL_64X),
260 GAIN_SCALE_GAIN(256, BU27010_GSEL_256X),
261 GAIN_SCALE_GAIN(1024, BU27010_GSEL_1024X),
262 GAIN_SCALE_GAIN(4096, BU27010_GSEL_4096X),
263 };
264
265 #define BU27008_MEAS_MODE_100MS 0x00
266 #define BU27008_MEAS_MODE_55MS 0x01
267 #define BU27008_MEAS_MODE_200MS 0x02
268 #define BU27008_MEAS_MODE_400MS 0x04
269
270 #define BU27010_MEAS_MODE_100MS 0x00
271 #define BU27010_MEAS_MODE_55MS 0x03
272 #define BU27010_MEAS_MODE_200MS 0x01
273 #define BU27010_MEAS_MODE_400MS 0x02
274
275 #define BU27008_MEAS_TIME_MAX_MS 400
276
277 static const struct iio_itime_sel_mul bu27008_itimes[] = {
278 GAIN_SCALE_ITIME_US(400000, BU27008_MEAS_MODE_400MS, 8),
279 GAIN_SCALE_ITIME_US(200000, BU27008_MEAS_MODE_200MS, 4),
280 GAIN_SCALE_ITIME_US(100000, BU27008_MEAS_MODE_100MS, 2),
281 GAIN_SCALE_ITIME_US(55000, BU27008_MEAS_MODE_55MS, 1),
282 };
283
284 static const struct iio_itime_sel_mul bu27010_itimes[] = {
285 GAIN_SCALE_ITIME_US(400000, BU27010_MEAS_MODE_400MS, 8),
286 GAIN_SCALE_ITIME_US(200000, BU27010_MEAS_MODE_200MS, 4),
287 GAIN_SCALE_ITIME_US(100000, BU27010_MEAS_MODE_100MS, 2),
288 GAIN_SCALE_ITIME_US(55000, BU27010_MEAS_MODE_55MS, 1),
289 };
290
291 /*
292 * All the RGBC channels share the same gain.
293 * IR gain can be fine-tuned from the gain set for the RGBC by 2 bit, but this
294 * would yield quite complex gain setting. Especially since not all bit
295 * compinations are supported. And in any case setting GAIN for RGBC will
296 * always also change the IR-gain.
297 *
298 * On top of this, the selector '0' which corresponds to hw-gain 1X on RGBC,
299 * corresponds to gain 2X on IR. Rest of the selctors correspond to same gains
300 * though. This, however, makes it not possible to use shared gain for all
301 * RGBC and IR settings even though they are all changed at the one go.
302 */
303 #define BU27008_CHAN(color, data, separate_avail) \
304 { \
305 .type = IIO_INTENSITY, \
306 .modified = 1, \
307 .channel2 = IIO_MOD_LIGHT_##color, \
308 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
309 BIT(IIO_CHAN_INFO_SCALE), \
310 .info_mask_separate_available = (separate_avail), \
311 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME), \
312 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME), \
313 .address = BU27008_REG_##data##_LO, \
314 .scan_index = BU27008_##color, \
315 .scan_type = { \
316 .sign = 'u', \
317 .realbits = 16, \
318 .storagebits = 16, \
319 .endianness = IIO_LE, \
320 }, \
321 }
322
323 /* For raw reads we always configure DATA3 for CLEAR */
324 static const struct iio_chan_spec bu27008_channels[] = {
325 BU27008_CHAN(RED, DATA0, BIT(IIO_CHAN_INFO_SCALE)),
326 BU27008_CHAN(GREEN, DATA1, BIT(IIO_CHAN_INFO_SCALE)),
327 BU27008_CHAN(BLUE, DATA2, BIT(IIO_CHAN_INFO_SCALE)),
328 BU27008_CHAN(CLEAR, DATA2, BIT(IIO_CHAN_INFO_SCALE)),
329 /*
330 * We don't allow setting scale for IR (because of shared gain bits).
331 * Hence we don't advertise available ones either.
332 */
333 BU27008_CHAN(IR, DATA3, 0),
334 IIO_CHAN_SOFT_TIMESTAMP(BU27008_NUM_CHANS),
335 };
336
337 struct bu27008_data;
338
339 struct bu27_chip_data {
340 const char *name;
341 int (*chip_init)(struct bu27008_data *data);
342 int (*get_gain_sel)(struct bu27008_data *data, int *sel);
343 int (*write_gain_sel)(struct bu27008_data *data, int sel);
344 const struct regmap_config *regmap_cfg;
345 const struct iio_gain_sel_pair *gains;
346 const struct iio_gain_sel_pair *gains_ir;
347 const struct iio_itime_sel_mul *itimes;
348 int num_gains;
349 int num_gains_ir;
350 int num_itimes;
351 int scale1x;
352
353 int drdy_en_reg;
354 int drdy_en_mask;
355 int meas_en_reg;
356 int meas_en_mask;
357 int valid_reg;
358 int chan_sel_reg;
359 int chan_sel_mask;
360 int int_time_mask;
361 u8 part_id;
362 };
363
364 struct bu27008_data {
365 const struct bu27_chip_data *cd;
366 struct regmap *regmap;
367 struct iio_trigger *trig;
368 struct device *dev;
369 struct iio_gts gts;
370 struct iio_gts gts_ir;
371 int irq;
372
373 /*
374 * Prevent changing gain/time config when scale is read/written.
375 * Similarly, protect the integration_time read/change sequence.
376 * Prevent changing gain/time when data is read.
377 */
378 struct mutex mutex;
379 };
380
381 static const struct regmap_range bu27008_volatile_ranges[] = {
382 {
383 .range_min = BU27008_REG_SYSTEM_CONTROL, /* SWRESET */
384 .range_max = BU27008_REG_SYSTEM_CONTROL,
385 }, {
386 .range_min = BU27008_REG_MODE_CONTROL3, /* VALID */
387 .range_max = BU27008_REG_MODE_CONTROL3,
388 }, {
389 .range_min = BU27008_REG_DATA0_LO, /* DATA */
390 .range_max = BU27008_REG_DATA3_HI,
391 },
392 };
393
394 static const struct regmap_range bu27010_volatile_ranges[] = {
395 {
396 .range_min = BU27010_REG_RESET, /* RSTB */
397 .range_max = BU27008_REG_SYSTEM_CONTROL, /* RESET */
398 }, {
399 .range_min = BU27010_REG_MODE_CONTROL5, /* VALID bits */
400 .range_max = BU27010_REG_MODE_CONTROL5,
401 }, {
402 .range_min = BU27008_REG_DATA0_LO,
403 .range_max = BU27010_REG_FIFO_DATA_HI,
404 },
405 };
406
407 static const struct regmap_access_table bu27008_volatile_regs = {
408 .yes_ranges = &bu27008_volatile_ranges[0],
409 .n_yes_ranges = ARRAY_SIZE(bu27008_volatile_ranges),
410 };
411
412 static const struct regmap_access_table bu27010_volatile_regs = {
413 .yes_ranges = &bu27010_volatile_ranges[0],
414 .n_yes_ranges = ARRAY_SIZE(bu27010_volatile_ranges),
415 };
416
417 static const struct regmap_range bu27008_read_only_ranges[] = {
418 {
419 .range_min = BU27008_REG_DATA0_LO,
420 .range_max = BU27008_REG_DATA3_HI,
421 }, {
422 .range_min = BU27008_REG_MANUFACTURER_ID,
423 .range_max = BU27008_REG_MANUFACTURER_ID,
424 },
425 };
426
427 static const struct regmap_range bu27010_read_only_ranges[] = {
428 {
429 .range_min = BU27008_REG_DATA0_LO,
430 .range_max = BU27010_REG_FIFO_DATA_HI,
431 }, {
432 .range_min = BU27010_REG_MANUFACTURER_ID,
433 .range_max = BU27010_REG_MANUFACTURER_ID,
434 }
435 };
436
437 static const struct regmap_access_table bu27008_ro_regs = {
438 .no_ranges = &bu27008_read_only_ranges[0],
439 .n_no_ranges = ARRAY_SIZE(bu27008_read_only_ranges),
440 };
441
442 static const struct regmap_access_table bu27010_ro_regs = {
443 .no_ranges = &bu27010_read_only_ranges[0],
444 .n_no_ranges = ARRAY_SIZE(bu27010_read_only_ranges),
445 };
446
447 static const struct regmap_config bu27008_regmap = {
448 .reg_bits = 8,
449 .val_bits = 8,
450 .max_register = BU27008_REG_MAX,
451 .cache_type = REGCACHE_RBTREE,
452 .volatile_table = &bu27008_volatile_regs,
453 .wr_table = &bu27008_ro_regs,
454 /*
455 * All register writes are serialized by the mutex which protects the
456 * scale setting/getting. This is needed because scale is combined by
457 * gain and integration time settings and we need to ensure those are
458 * not read / written when scale is being computed.
459 *
460 * As a result of this serializing, we don't need regmap locking. Note,
461 * this is not true if we add any configurations which are not
462 * serialized by the mutex and which may need for example a protected
463 * read-modify-write cycle (eg. regmap_update_bits()). Please, revise
464 * this when adding features to the driver.
465 */
466 .disable_locking = true,
467 };
468
469 static const struct regmap_config bu27010_regmap = {
470 .reg_bits = 8,
471 .val_bits = 8,
472
473 .max_register = BU27010_REG_MAX,
474 .cache_type = REGCACHE_RBTREE,
475 .volatile_table = &bu27010_volatile_regs,
476 .wr_table = &bu27010_ro_regs,
477 .disable_locking = true,
478 };
479
bu27008_write_gain_sel(struct bu27008_data * data,int sel)480 static int bu27008_write_gain_sel(struct bu27008_data *data, int sel)
481 {
482 int regval;
483
484 regval = FIELD_PREP(BU27008_MASK_RGBC_GAIN, sel);
485
486 /*
487 * We do always set also the LOW bits of IR-gain because othervice we
488 * would risk resulting an invalid GAIN register value.
489 *
490 * We could allow setting separate gains for RGBC and IR when the
491 * values were such that HW could support both gain settings.
492 * Eg, when the shared bits were same for both gain values.
493 *
494 * This, however, has a negligible benefit compared to the increased
495 * software complexity when we would need to go through the gains
496 * for both channels separately when the integration time changes.
497 * This would end up with nasty logic for computing gain values for
498 * both channels - and rejecting them if shared bits changed.
499 *
500 * We should then build the logic by guessing what a user prefers.
501 * RGBC or IR gains correctly set while other jumps to odd value?
502 * Maybe look-up a value where both gains are somehow optimized
503 * <what this somehow is, is ATM unknown to us>. Or maybe user would
504 * expect us to reject changes when optimal gains can't be set to both
505 * channels w/given integration time. At best that would result
506 * solution that works well for a very specific subset of
507 * configurations but causes unexpected corner-cases.
508 *
509 * So, we keep it simple. Always set same selector to IR and RGBC.
510 * We disallow setting IR (as I expect that most of the users are
511 * interested in RGBC). This way we can show the user that the scales
512 * for RGBC and IR channels are different (1X Vs 2X with sel 0) while
513 * still keeping the operation deterministic.
514 */
515 regval |= FIELD_PREP(BU27008_MASK_IR_GAIN_LO, sel);
516
517 return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL2,
518 BU27008_MASK_RGBC_GAIN, regval);
519 }
520
bu27010_write_gain_sel(struct bu27008_data * data,int sel)521 static int bu27010_write_gain_sel(struct bu27008_data *data, int sel)
522 {
523 unsigned int regval;
524 int ret, chan_selector;
525
526 /*
527 * Gain 'selector' is composed of two registers. Selector is 6bit value,
528 * 4 high bits being the RGBC gain fieild in MODE_CONTROL1 register and
529 * two low bits being the channel specific gain in MODE_CONTROL2.
530 *
531 * Let's take the 4 high bits of whole 6 bit selector, and prepare
532 * the MODE_CONTROL1 value (RGBC gain part).
533 */
534 regval = FIELD_PREP(BU27010_MASK_RGBC_GAIN, (sel >> 2));
535
536 ret = regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1,
537 BU27010_MASK_RGBC_GAIN, regval);
538 if (ret)
539 return ret;
540
541 /*
542 * Two low two bits of the selector must be written for all 4
543 * channels in the MODE_CONTROL2 register. Copy these two bits for
544 * all channels.
545 */
546 chan_selector = sel & GENMASK(1, 0);
547
548 regval = FIELD_PREP(BU27010_MASK_DATA0_GAIN, chan_selector);
549 regval |= FIELD_PREP(BU27010_MASK_DATA1_GAIN, chan_selector);
550 regval |= FIELD_PREP(BU27010_MASK_DATA2_GAIN, chan_selector);
551 regval |= FIELD_PREP(BU27010_MASK_DATA3_GAIN, chan_selector);
552
553 return regmap_write(data->regmap, BU27008_REG_MODE_CONTROL2, regval);
554 }
555
bu27008_get_gain_sel(struct bu27008_data * data,int * sel)556 static int bu27008_get_gain_sel(struct bu27008_data *data, int *sel)
557 {
558 int ret;
559
560 /*
561 * If we always "lock" the gain selectors for all channels to prevent
562 * unsupported configs, then it does not matter which channel is used
563 * we can just return selector from any of them.
564 *
565 * This, however is not true if we decide to support only 4X and 16X
566 * and then individual gains for channels. Currently this is not the
567 * case.
568 *
569 * If we some day decide to support individual gains, then we need to
570 * have channel information here.
571 */
572
573 ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, sel);
574 if (ret)
575 return ret;
576
577 *sel = FIELD_GET(BU27008_MASK_RGBC_GAIN, *sel);
578
579 return 0;
580 }
581
bu27010_get_gain_sel(struct bu27008_data * data,int * sel)582 static int bu27010_get_gain_sel(struct bu27008_data *data, int *sel)
583 {
584 int ret, tmp;
585
586 /*
587 * We always "lock" the gain selectors for all channels to prevent
588 * unsupported configs. It does not matter which channel is used
589 * we can just return selector from any of them.
590 *
591 * Read the channel0 gain.
592 */
593 ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, sel);
594 if (ret)
595 return ret;
596
597 *sel = FIELD_GET(BU27010_MASK_DATA0_GAIN, *sel);
598
599 /* Read the shared gain */
600 ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL1, &tmp);
601 if (ret)
602 return ret;
603
604 /*
605 * The gain selector is made as a combination of common RGBC gain and
606 * the channel specific gain. The channel specific gain forms the low
607 * bits of selector and RGBC gain is appended right after it.
608 *
609 * Compose the selector from channel0 gain and shared RGBC gain.
610 */
611 *sel |= FIELD_GET(BU27010_MASK_RGBC_GAIN, tmp) << fls(BU27010_MASK_DATA0_GAIN);
612
613 return ret;
614 }
615
bu27008_chip_init(struct bu27008_data * data)616 static int bu27008_chip_init(struct bu27008_data *data)
617 {
618 int ret;
619
620 ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL,
621 BU27008_MASK_SW_RESET, BU27008_MASK_SW_RESET);
622 if (ret)
623 return dev_err_probe(data->dev, ret, "Sensor reset failed\n");
624
625 /*
626 * The data-sheet does not tell how long performing the IC reset takes.
627 * However, the data-sheet says the minimum time it takes the IC to be
628 * able to take inputs after power is applied, is 100 uS. I'd assume
629 * > 1 mS is enough.
630 */
631 msleep(1);
632
633 ret = regmap_reinit_cache(data->regmap, data->cd->regmap_cfg);
634 if (ret)
635 dev_err(data->dev, "Failed to reinit reg cache\n");
636
637 return ret;
638 }
639
bu27010_chip_init(struct bu27008_data * data)640 static int bu27010_chip_init(struct bu27008_data *data)
641 {
642 int ret;
643
644 ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL,
645 BU27010_MASK_SW_RESET, BU27010_MASK_SW_RESET);
646 if (ret)
647 return dev_err_probe(data->dev, ret, "Sensor reset failed\n");
648
649 msleep(1);
650
651 /* Power ON*/
652 ret = regmap_write_bits(data->regmap, BU27010_REG_POWER,
653 BU27010_MASK_POWER, BU27010_MASK_POWER);
654 if (ret)
655 return dev_err_probe(data->dev, ret, "Sensor power-on failed\n");
656
657 msleep(1);
658
659 /* Release blocks from reset */
660 ret = regmap_write_bits(data->regmap, BU27010_REG_RESET,
661 BU27010_MASK_RESET, BU27010_RESET_RELEASE);
662 if (ret)
663 return dev_err_probe(data->dev, ret, "Sensor powering failed\n");
664
665 msleep(1);
666
667 /*
668 * The IRQ enabling on BU27010 is done in a peculiar way. The IRQ
669 * enabling is not a bit mask where individual IRQs could be enabled but
670 * a field which values are:
671 * 00 => IRQs disabled
672 * 01 => Data-ready (RGBC/IR)
673 * 10 => Data-ready (flicker)
674 * 11 => Flicker FIFO
675 *
676 * So, only one IRQ can be enabled at a time and enabling for example
677 * flicker FIFO would automagically disable data-ready IRQ.
678 *
679 * Currently the driver does not support the flicker. Hence, we can
680 * just treat the RGBC data-ready as single bit which can be enabled /
681 * disabled. This works for as long as the second bit in the field
682 * stays zero. Here we ensure it gets zeroed.
683 */
684 return regmap_clear_bits(data->regmap, BU27010_REG_MODE_CONTROL4,
685 BU27010_IRQ_DIS_ALL);
686 }
687
688 static const struct bu27_chip_data bu27010_chip = {
689 .name = "bu27010",
690 .chip_init = bu27010_chip_init,
691 .get_gain_sel = bu27010_get_gain_sel,
692 .write_gain_sel = bu27010_write_gain_sel,
693 .regmap_cfg = &bu27010_regmap,
694 .gains = &bu27010_gains[0],
695 .gains_ir = &bu27010_gains_ir[0],
696 .itimes = &bu27010_itimes[0],
697 .num_gains = ARRAY_SIZE(bu27010_gains),
698 .num_gains_ir = ARRAY_SIZE(bu27010_gains_ir),
699 .num_itimes = ARRAY_SIZE(bu27010_itimes),
700 .scale1x = BU27010_SCALE_1X,
701 .drdy_en_reg = BU27010_REG_MODE_CONTROL4,
702 .drdy_en_mask = BU27010_DRDY_EN,
703 .meas_en_reg = BU27010_REG_MODE_CONTROL5,
704 .meas_en_mask = BU27010_MASK_MEAS_EN,
705 .valid_reg = BU27010_REG_MODE_CONTROL5,
706 .chan_sel_reg = BU27008_REG_MODE_CONTROL1,
707 .chan_sel_mask = BU27010_MASK_CHAN_SEL,
708 .int_time_mask = BU27010_MASK_MEAS_MODE,
709 .part_id = BU27010_ID,
710 };
711
712 static const struct bu27_chip_data bu27008_chip = {
713 .name = "bu27008",
714 .chip_init = bu27008_chip_init,
715 .get_gain_sel = bu27008_get_gain_sel,
716 .write_gain_sel = bu27008_write_gain_sel,
717 .regmap_cfg = &bu27008_regmap,
718 .gains = &bu27008_gains[0],
719 .gains_ir = &bu27008_gains_ir[0],
720 .itimes = &bu27008_itimes[0],
721 .num_gains = ARRAY_SIZE(bu27008_gains),
722 .num_gains_ir = ARRAY_SIZE(bu27008_gains_ir),
723 .num_itimes = ARRAY_SIZE(bu27008_itimes),
724 .scale1x = BU27008_SCALE_1X,
725 .drdy_en_reg = BU27008_REG_MODE_CONTROL3,
726 .drdy_en_mask = BU27008_MASK_INT_EN,
727 .valid_reg = BU27008_REG_MODE_CONTROL3,
728 .meas_en_reg = BU27008_REG_MODE_CONTROL3,
729 .meas_en_mask = BU27008_MASK_MEAS_EN,
730 .chan_sel_reg = BU27008_REG_MODE_CONTROL3,
731 .chan_sel_mask = BU27008_MASK_CHAN_SEL,
732 .int_time_mask = BU27008_MASK_MEAS_MODE,
733 .part_id = BU27008_ID,
734 };
735
736 #define BU27008_MAX_VALID_RESULT_WAIT_US 50000
737 #define BU27008_VALID_RESULT_WAIT_QUANTA_US 1000
738
bu27008_chan_read_data(struct bu27008_data * data,int reg,int * val)739 static int bu27008_chan_read_data(struct bu27008_data *data, int reg, int *val)
740 {
741 int ret, valid;
742 __le16 tmp;
743
744 ret = regmap_read_poll_timeout(data->regmap, data->cd->valid_reg,
745 valid, (valid & BU27008_MASK_VALID),
746 BU27008_VALID_RESULT_WAIT_QUANTA_US,
747 BU27008_MAX_VALID_RESULT_WAIT_US);
748 if (ret)
749 return ret;
750
751 ret = regmap_bulk_read(data->regmap, reg, &tmp, sizeof(tmp));
752 if (ret)
753 dev_err(data->dev, "Reading channel data failed\n");
754
755 *val = le16_to_cpu(tmp);
756
757 return ret;
758 }
759
bu27008_get_gain(struct bu27008_data * data,struct iio_gts * gts,int * gain)760 static int bu27008_get_gain(struct bu27008_data *data, struct iio_gts *gts, int *gain)
761 {
762 int ret, sel;
763
764 ret = data->cd->get_gain_sel(data, &sel);
765 if (ret)
766 return ret;
767
768 ret = iio_gts_find_gain_by_sel(gts, sel);
769 if (ret < 0) {
770 dev_err(data->dev, "unknown gain value 0x%x\n", sel);
771 return ret;
772 }
773
774 *gain = ret;
775
776 return 0;
777 }
778
bu27008_set_gain(struct bu27008_data * data,int gain)779 static int bu27008_set_gain(struct bu27008_data *data, int gain)
780 {
781 int ret;
782
783 ret = iio_gts_find_sel_by_gain(&data->gts, gain);
784 if (ret < 0)
785 return ret;
786
787 return data->cd->write_gain_sel(data, ret);
788 }
789
bu27008_get_int_time_sel(struct bu27008_data * data,int * sel)790 static int bu27008_get_int_time_sel(struct bu27008_data *data, int *sel)
791 {
792 int ret, val;
793
794 ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL1, &val);
795 if (ret)
796 return ret;
797
798 val &= data->cd->int_time_mask;
799 val >>= ffs(data->cd->int_time_mask) - 1;
800
801 *sel = val;
802
803 return 0;
804 }
805
bu27008_set_int_time_sel(struct bu27008_data * data,int sel)806 static int bu27008_set_int_time_sel(struct bu27008_data *data, int sel)
807 {
808 sel <<= ffs(data->cd->int_time_mask) - 1;
809
810 return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1,
811 data->cd->int_time_mask, sel);
812 }
813
bu27008_get_int_time_us(struct bu27008_data * data)814 static int bu27008_get_int_time_us(struct bu27008_data *data)
815 {
816 int ret, sel;
817
818 ret = bu27008_get_int_time_sel(data, &sel);
819 if (ret)
820 return ret;
821
822 return iio_gts_find_int_time_by_sel(&data->gts, sel);
823 }
824
_bu27008_get_scale(struct bu27008_data * data,bool ir,int * val,int * val2)825 static int _bu27008_get_scale(struct bu27008_data *data, bool ir, int *val,
826 int *val2)
827 {
828 struct iio_gts *gts;
829 int gain, ret;
830
831 if (ir)
832 gts = &data->gts_ir;
833 else
834 gts = &data->gts;
835
836 ret = bu27008_get_gain(data, gts, &gain);
837 if (ret)
838 return ret;
839
840 ret = bu27008_get_int_time_us(data);
841 if (ret < 0)
842 return ret;
843
844 return iio_gts_get_scale(gts, gain, ret, val, val2);
845 }
846
bu27008_get_scale(struct bu27008_data * data,bool ir,int * val,int * val2)847 static int bu27008_get_scale(struct bu27008_data *data, bool ir, int *val,
848 int *val2)
849 {
850 int ret;
851
852 mutex_lock(&data->mutex);
853 ret = _bu27008_get_scale(data, ir, val, val2);
854 mutex_unlock(&data->mutex);
855
856 return ret;
857 }
858
bu27008_set_int_time(struct bu27008_data * data,int time)859 static int bu27008_set_int_time(struct bu27008_data *data, int time)
860 {
861 int ret;
862
863 ret = iio_gts_find_sel_by_int_time(&data->gts, time);
864 if (ret < 0)
865 return ret;
866
867 return bu27008_set_int_time_sel(data, ret);
868 }
869
870 /* Try to change the time so that the scale is maintained */
bu27008_try_set_int_time(struct bu27008_data * data,int int_time_new)871 static int bu27008_try_set_int_time(struct bu27008_data *data, int int_time_new)
872 {
873 int ret, old_time_sel, new_time_sel, old_gain, new_gain;
874
875 mutex_lock(&data->mutex);
876
877 ret = bu27008_get_int_time_sel(data, &old_time_sel);
878 if (ret < 0)
879 goto unlock_out;
880
881 if (!iio_gts_valid_time(&data->gts, int_time_new)) {
882 dev_dbg(data->dev, "Unsupported integration time %u\n",
883 int_time_new);
884
885 ret = -EINVAL;
886 goto unlock_out;
887 }
888
889 /* If we already use requested time, then we're done */
890 new_time_sel = iio_gts_find_sel_by_int_time(&data->gts, int_time_new);
891 if (new_time_sel == old_time_sel)
892 goto unlock_out;
893
894 ret = bu27008_get_gain(data, &data->gts, &old_gain);
895 if (ret)
896 goto unlock_out;
897
898 ret = iio_gts_find_new_gain_sel_by_old_gain_time(&data->gts, old_gain,
899 old_time_sel, new_time_sel, &new_gain);
900 if (ret) {
901 int scale1, scale2;
902 bool ok;
903
904 _bu27008_get_scale(data, false, &scale1, &scale2);
905 dev_dbg(data->dev,
906 "Can't support time %u with current scale %u %u\n",
907 int_time_new, scale1, scale2);
908
909 if (new_gain < 0)
910 goto unlock_out;
911
912 /*
913 * If caller requests for integration time change and we
914 * can't support the scale - then the caller should be
915 * prepared to 'pick up the pieces and deal with the
916 * fact that the scale changed'.
917 */
918 ret = iio_find_closest_gain_low(&data->gts, new_gain, &ok);
919 if (!ok)
920 dev_dbg(data->dev, "optimal gain out of range\n");
921
922 if (ret < 0) {
923 dev_dbg(data->dev,
924 "Total gain increase. Risk of saturation");
925 ret = iio_gts_get_min_gain(&data->gts);
926 if (ret < 0)
927 goto unlock_out;
928 }
929 new_gain = ret;
930 dev_dbg(data->dev, "scale changed, new gain %u\n", new_gain);
931 }
932
933 ret = bu27008_set_gain(data, new_gain);
934 if (ret)
935 goto unlock_out;
936
937 ret = bu27008_set_int_time(data, int_time_new);
938
939 unlock_out:
940 mutex_unlock(&data->mutex);
941
942 return ret;
943 }
944
bu27008_meas_set(struct bu27008_data * data,bool enable)945 static int bu27008_meas_set(struct bu27008_data *data, bool enable)
946 {
947 if (enable)
948 return regmap_set_bits(data->regmap, data->cd->meas_en_reg,
949 data->cd->meas_en_mask);
950 return regmap_clear_bits(data->regmap, data->cd->meas_en_reg,
951 data->cd->meas_en_mask);
952 }
953
bu27008_chan_cfg(struct bu27008_data * data,struct iio_chan_spec const * chan)954 static int bu27008_chan_cfg(struct bu27008_data *data,
955 struct iio_chan_spec const *chan)
956 {
957 int chan_sel;
958
959 if (chan->scan_index == BU27008_BLUE)
960 chan_sel = BU27008_BLUE2_CLEAR3;
961 else
962 chan_sel = BU27008_CLEAR2_IR3;
963
964 /*
965 * prepare bitfield for channel sel. The FIELD_PREP works only when
966 * mask is constant. In our case the mask is assigned based on the
967 * chip type. Hence the open-coded FIELD_PREP here. We don't bother
968 * zeroing the irrelevant bits though - update_bits takes care of that.
969 */
970 chan_sel <<= ffs(data->cd->chan_sel_mask) - 1;
971
972 return regmap_update_bits(data->regmap, data->cd->chan_sel_reg,
973 BU27008_MASK_CHAN_SEL, chan_sel);
974 }
975
bu27008_read_one(struct bu27008_data * data,struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2)976 static int bu27008_read_one(struct bu27008_data *data, struct iio_dev *idev,
977 struct iio_chan_spec const *chan, int *val, int *val2)
978 {
979 int ret, int_time;
980
981 ret = bu27008_chan_cfg(data, chan);
982 if (ret)
983 return ret;
984
985 ret = bu27008_meas_set(data, true);
986 if (ret)
987 return ret;
988
989 ret = bu27008_get_int_time_us(data);
990 if (ret < 0)
991 int_time = BU27008_MEAS_TIME_MAX_MS;
992 else
993 int_time = ret / USEC_PER_MSEC;
994
995 msleep(int_time);
996
997 ret = bu27008_chan_read_data(data, chan->address, val);
998 if (!ret)
999 ret = IIO_VAL_INT;
1000
1001 if (bu27008_meas_set(data, false))
1002 dev_warn(data->dev, "measurement disabling failed\n");
1003
1004 return ret;
1005 }
1006
bu27008_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)1007 static int bu27008_read_raw(struct iio_dev *idev,
1008 struct iio_chan_spec const *chan,
1009 int *val, int *val2, long mask)
1010 {
1011 struct bu27008_data *data = iio_priv(idev);
1012 int busy, ret;
1013
1014 switch (mask) {
1015 case IIO_CHAN_INFO_RAW:
1016 busy = iio_device_claim_direct_mode(idev);
1017 if (busy)
1018 return -EBUSY;
1019
1020 mutex_lock(&data->mutex);
1021 ret = bu27008_read_one(data, idev, chan, val, val2);
1022 mutex_unlock(&data->mutex);
1023
1024 iio_device_release_direct_mode(idev);
1025
1026 return ret;
1027
1028 case IIO_CHAN_INFO_SCALE:
1029 ret = bu27008_get_scale(data, chan->scan_index == BU27008_IR,
1030 val, val2);
1031 if (ret)
1032 return ret;
1033
1034 return IIO_VAL_INT_PLUS_NANO;
1035
1036 case IIO_CHAN_INFO_INT_TIME:
1037 ret = bu27008_get_int_time_us(data);
1038 if (ret < 0)
1039 return ret;
1040
1041 *val = 0;
1042 *val2 = ret;
1043
1044 return IIO_VAL_INT_PLUS_MICRO;
1045
1046 default:
1047 return -EINVAL;
1048 }
1049 }
1050
1051 /* Called if the new scale could not be supported with existing int-time */
bu27008_try_find_new_time_gain(struct bu27008_data * data,int val,int val2,int * gain_sel)1052 static int bu27008_try_find_new_time_gain(struct bu27008_data *data, int val,
1053 int val2, int *gain_sel)
1054 {
1055 int i, ret, new_time_sel;
1056
1057 for (i = 0; i < data->gts.num_itime; i++) {
1058 new_time_sel = data->gts.itime_table[i].sel;
1059 ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts,
1060 new_time_sel, val, val2, gain_sel);
1061 if (!ret)
1062 break;
1063 }
1064 if (i == data->gts.num_itime) {
1065 dev_err(data->dev, "Can't support scale %u %u\n", val, val2);
1066
1067 return -EINVAL;
1068 }
1069
1070 return bu27008_set_int_time_sel(data, new_time_sel);
1071 }
1072
bu27008_set_scale(struct bu27008_data * data,struct iio_chan_spec const * chan,int val,int val2)1073 static int bu27008_set_scale(struct bu27008_data *data,
1074 struct iio_chan_spec const *chan,
1075 int val, int val2)
1076 {
1077 int ret, gain_sel, time_sel;
1078
1079 if (chan->scan_index == BU27008_IR)
1080 return -EINVAL;
1081
1082 mutex_lock(&data->mutex);
1083
1084 ret = bu27008_get_int_time_sel(data, &time_sel);
1085 if (ret < 0)
1086 goto unlock_out;
1087
1088 ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel,
1089 val, val2, &gain_sel);
1090 if (ret) {
1091 ret = bu27008_try_find_new_time_gain(data, val, val2, &gain_sel);
1092 if (ret)
1093 goto unlock_out;
1094
1095 }
1096 ret = data->cd->write_gain_sel(data, gain_sel);
1097
1098 unlock_out:
1099 mutex_unlock(&data->mutex);
1100
1101 return ret;
1102 }
1103
bu27008_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1104 static int bu27008_write_raw_get_fmt(struct iio_dev *indio_dev,
1105 struct iio_chan_spec const *chan,
1106 long mask)
1107 {
1108
1109 switch (mask) {
1110 case IIO_CHAN_INFO_SCALE:
1111 return IIO_VAL_INT_PLUS_NANO;
1112 case IIO_CHAN_INFO_INT_TIME:
1113 return IIO_VAL_INT_PLUS_MICRO;
1114 default:
1115 return -EINVAL;
1116 }
1117 }
1118
bu27008_write_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int val,int val2,long mask)1119 static int bu27008_write_raw(struct iio_dev *idev,
1120 struct iio_chan_spec const *chan,
1121 int val, int val2, long mask)
1122 {
1123 struct bu27008_data *data = iio_priv(idev);
1124 int ret;
1125
1126 /*
1127 * Do not allow changing scale when measurement is ongoing as doing so
1128 * could make values in the buffer inconsistent.
1129 */
1130 ret = iio_device_claim_direct_mode(idev);
1131 if (ret)
1132 return ret;
1133
1134 switch (mask) {
1135 case IIO_CHAN_INFO_SCALE:
1136 ret = bu27008_set_scale(data, chan, val, val2);
1137 break;
1138 case IIO_CHAN_INFO_INT_TIME:
1139 if (val) {
1140 ret = -EINVAL;
1141 break;
1142 }
1143 ret = bu27008_try_set_int_time(data, val2);
1144 break;
1145 default:
1146 ret = -EINVAL;
1147 break;
1148 }
1149 iio_device_release_direct_mode(idev);
1150
1151 return ret;
1152 }
1153
bu27008_read_avail(struct iio_dev * idev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1154 static int bu27008_read_avail(struct iio_dev *idev,
1155 struct iio_chan_spec const *chan, const int **vals,
1156 int *type, int *length, long mask)
1157 {
1158 struct bu27008_data *data = iio_priv(idev);
1159
1160 switch (mask) {
1161 case IIO_CHAN_INFO_INT_TIME:
1162 return iio_gts_avail_times(&data->gts, vals, type, length);
1163 case IIO_CHAN_INFO_SCALE:
1164 if (chan->channel2 == IIO_MOD_LIGHT_IR)
1165 return iio_gts_all_avail_scales(&data->gts_ir, vals,
1166 type, length);
1167 return iio_gts_all_avail_scales(&data->gts, vals, type, length);
1168 default:
1169 return -EINVAL;
1170 }
1171 }
1172
bu27008_update_scan_mode(struct iio_dev * idev,const unsigned long * scan_mask)1173 static int bu27008_update_scan_mode(struct iio_dev *idev,
1174 const unsigned long *scan_mask)
1175 {
1176 struct bu27008_data *data = iio_priv(idev);
1177 int chan_sel;
1178
1179 /* Configure channel selection */
1180 if (test_bit(BU27008_BLUE, idev->active_scan_mask)) {
1181 if (test_bit(BU27008_CLEAR, idev->active_scan_mask))
1182 chan_sel = BU27008_BLUE2_CLEAR3;
1183 else
1184 chan_sel = BU27008_BLUE2_IR3;
1185 } else {
1186 chan_sel = BU27008_CLEAR2_IR3;
1187 }
1188
1189 chan_sel <<= ffs(data->cd->chan_sel_mask) - 1;
1190
1191 return regmap_update_bits(data->regmap, data->cd->chan_sel_reg,
1192 data->cd->chan_sel_mask, chan_sel);
1193 }
1194
1195 static const struct iio_info bu27008_info = {
1196 .read_raw = &bu27008_read_raw,
1197 .write_raw = &bu27008_write_raw,
1198 .write_raw_get_fmt = &bu27008_write_raw_get_fmt,
1199 .read_avail = &bu27008_read_avail,
1200 .update_scan_mode = bu27008_update_scan_mode,
1201 .validate_trigger = iio_validate_own_trigger,
1202 };
1203
bu27008_trigger_set_state(struct iio_trigger * trig,bool state)1204 static int bu27008_trigger_set_state(struct iio_trigger *trig, bool state)
1205 {
1206 struct bu27008_data *data = iio_trigger_get_drvdata(trig);
1207 int ret;
1208
1209
1210 if (state)
1211 ret = regmap_set_bits(data->regmap, data->cd->drdy_en_reg,
1212 data->cd->drdy_en_mask);
1213 else
1214 ret = regmap_clear_bits(data->regmap, data->cd->drdy_en_reg,
1215 data->cd->drdy_en_mask);
1216 if (ret)
1217 dev_err(data->dev, "Failed to set trigger state\n");
1218
1219 return ret;
1220 }
1221
bu27008_trigger_reenable(struct iio_trigger * trig)1222 static void bu27008_trigger_reenable(struct iio_trigger *trig)
1223 {
1224 struct bu27008_data *data = iio_trigger_get_drvdata(trig);
1225
1226 enable_irq(data->irq);
1227 }
1228
1229 static const struct iio_trigger_ops bu27008_trigger_ops = {
1230 .set_trigger_state = bu27008_trigger_set_state,
1231 .reenable = bu27008_trigger_reenable,
1232 };
1233
bu27008_trigger_handler(int irq,void * p)1234 static irqreturn_t bu27008_trigger_handler(int irq, void *p)
1235 {
1236 struct iio_poll_func *pf = p;
1237 struct iio_dev *idev = pf->indio_dev;
1238 struct bu27008_data *data = iio_priv(idev);
1239 struct {
1240 __le16 chan[BU27008_NUM_HW_CHANS];
1241 s64 ts __aligned(8);
1242 } raw;
1243 int ret, dummy;
1244
1245 memset(&raw, 0, sizeof(raw));
1246
1247 /*
1248 * After some measurements, it seems reading the
1249 * BU27008_REG_MODE_CONTROL3 debounces the IRQ line
1250 */
1251 ret = regmap_read(data->regmap, data->cd->valid_reg, &dummy);
1252 if (ret < 0)
1253 goto err_read;
1254
1255 ret = regmap_bulk_read(data->regmap, BU27008_REG_DATA0_LO, &raw.chan,
1256 sizeof(raw.chan));
1257 if (ret < 0)
1258 goto err_read;
1259
1260 iio_push_to_buffers_with_timestamp(idev, &raw, pf->timestamp);
1261 err_read:
1262 iio_trigger_notify_done(idev->trig);
1263
1264 return IRQ_HANDLED;
1265 }
1266
bu27008_buffer_preenable(struct iio_dev * idev)1267 static int bu27008_buffer_preenable(struct iio_dev *idev)
1268 {
1269 struct bu27008_data *data = iio_priv(idev);
1270
1271 return bu27008_meas_set(data, true);
1272 }
1273
bu27008_buffer_postdisable(struct iio_dev * idev)1274 static int bu27008_buffer_postdisable(struct iio_dev *idev)
1275 {
1276 struct bu27008_data *data = iio_priv(idev);
1277
1278 return bu27008_meas_set(data, false);
1279 }
1280
1281 static const struct iio_buffer_setup_ops bu27008_buffer_ops = {
1282 .preenable = bu27008_buffer_preenable,
1283 .postdisable = bu27008_buffer_postdisable,
1284 };
1285
bu27008_data_rdy_poll(int irq,void * private)1286 static irqreturn_t bu27008_data_rdy_poll(int irq, void *private)
1287 {
1288 /*
1289 * The BU27008 keeps IRQ asserted until we read the VALID bit from
1290 * a register. We need to keep the IRQ disabled until then.
1291 */
1292 disable_irq_nosync(irq);
1293 iio_trigger_poll(private);
1294
1295 return IRQ_HANDLED;
1296 }
1297
bu27008_setup_trigger(struct bu27008_data * data,struct iio_dev * idev)1298 static int bu27008_setup_trigger(struct bu27008_data *data, struct iio_dev *idev)
1299 {
1300 struct iio_trigger *itrig;
1301 char *name;
1302 int ret;
1303
1304 ret = devm_iio_triggered_buffer_setup(data->dev, idev,
1305 &iio_pollfunc_store_time,
1306 bu27008_trigger_handler,
1307 &bu27008_buffer_ops);
1308 if (ret)
1309 return dev_err_probe(data->dev, ret,
1310 "iio_triggered_buffer_setup_ext FAIL\n");
1311
1312 itrig = devm_iio_trigger_alloc(data->dev, "%sdata-rdy-dev%d",
1313 idev->name, iio_device_id(idev));
1314 if (!itrig)
1315 return -ENOMEM;
1316
1317 data->trig = itrig;
1318
1319 itrig->ops = &bu27008_trigger_ops;
1320 iio_trigger_set_drvdata(itrig, data);
1321
1322 name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-bu27008",
1323 dev_name(data->dev));
1324
1325 ret = devm_request_irq(data->dev, data->irq,
1326 &bu27008_data_rdy_poll,
1327 0, name, itrig);
1328 if (ret)
1329 return dev_err_probe(data->dev, ret, "Could not request IRQ\n");
1330
1331 ret = devm_iio_trigger_register(data->dev, itrig);
1332 if (ret)
1333 return dev_err_probe(data->dev, ret,
1334 "Trigger registration failed\n");
1335
1336 /* set default trigger */
1337 idev->trig = iio_trigger_get(itrig);
1338
1339 return 0;
1340 }
1341
bu27008_probe(struct i2c_client * i2c)1342 static int bu27008_probe(struct i2c_client *i2c)
1343 {
1344 struct device *dev = &i2c->dev;
1345 struct bu27008_data *data;
1346 struct regmap *regmap;
1347 unsigned int part_id, reg;
1348 struct iio_dev *idev;
1349 int ret;
1350
1351 idev = devm_iio_device_alloc(dev, sizeof(*data));
1352 if (!idev)
1353 return -ENOMEM;
1354
1355 ret = devm_regulator_get_enable(dev, "vdd");
1356 if (ret)
1357 return dev_err_probe(dev, ret, "Failed to get regulator\n");
1358
1359 data = iio_priv(idev);
1360
1361 data->cd = device_get_match_data(&i2c->dev);
1362 if (!data->cd)
1363 return -ENODEV;
1364
1365 regmap = devm_regmap_init_i2c(i2c, data->cd->regmap_cfg);
1366 if (IS_ERR(regmap))
1367 return dev_err_probe(dev, PTR_ERR(regmap),
1368 "Failed to initialize Regmap\n");
1369
1370
1371 ret = regmap_read(regmap, BU27008_REG_SYSTEM_CONTROL, ®);
1372 if (ret)
1373 return dev_err_probe(dev, ret, "Failed to access sensor\n");
1374
1375 part_id = FIELD_GET(BU27008_MASK_PART_ID, reg);
1376
1377 if (part_id != data->cd->part_id)
1378 dev_warn(dev, "unknown device 0x%x\n", part_id);
1379
1380 ret = devm_iio_init_iio_gts(dev, data->cd->scale1x, 0, data->cd->gains,
1381 data->cd->num_gains, data->cd->itimes,
1382 data->cd->num_itimes, &data->gts);
1383 if (ret)
1384 return ret;
1385
1386 ret = devm_iio_init_iio_gts(dev, data->cd->scale1x, 0, data->cd->gains_ir,
1387 data->cd->num_gains_ir, data->cd->itimes,
1388 data->cd->num_itimes, &data->gts_ir);
1389 if (ret)
1390 return ret;
1391
1392 mutex_init(&data->mutex);
1393 data->regmap = regmap;
1394 data->dev = dev;
1395 data->irq = i2c->irq;
1396
1397 idev->channels = bu27008_channels;
1398 idev->num_channels = ARRAY_SIZE(bu27008_channels);
1399 idev->name = data->cd->name;
1400 idev->info = &bu27008_info;
1401 idev->modes = INDIO_DIRECT_MODE;
1402 idev->available_scan_masks = bu27008_scan_masks;
1403
1404 ret = data->cd->chip_init(data);
1405 if (ret)
1406 return ret;
1407
1408 if (i2c->irq) {
1409 ret = bu27008_setup_trigger(data, idev);
1410 if (ret)
1411 return ret;
1412 } else {
1413 dev_info(dev, "No IRQ, buffered mode disabled\n");
1414 }
1415
1416 ret = devm_iio_device_register(dev, idev);
1417 if (ret)
1418 return dev_err_probe(dev, ret,
1419 "Unable to register iio device\n");
1420
1421 return 0;
1422 }
1423
1424 static const struct of_device_id bu27008_of_match[] = {
1425 { .compatible = "rohm,bu27008", .data = &bu27008_chip },
1426 { .compatible = "rohm,bu27010", .data = &bu27010_chip },
1427 { }
1428 };
1429 MODULE_DEVICE_TABLE(of, bu27008_of_match);
1430
1431 static struct i2c_driver bu27008_i2c_driver = {
1432 .driver = {
1433 .name = "bu27008",
1434 .of_match_table = bu27008_of_match,
1435 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1436 },
1437 .probe = bu27008_probe,
1438 };
1439 module_i2c_driver(bu27008_i2c_driver);
1440
1441 MODULE_DESCRIPTION("ROHM BU27008 and BU27010 colour sensor driver");
1442 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
1443 MODULE_LICENSE("GPL");
1444 MODULE_IMPORT_NS(IIO_GTS_HELPER);
1445
