Searched refs:BIT12 (Results 1 – 15 of 15) sorted by relevance
69 #define RCR_AICV BIT12110 #define IMR_RXFOVW BIT12
43 #define BIT12 0x00001000 macro
203 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */
29 #define BIT12 0x00001000 macro
559 #define RRSR_MCS0 BIT12703 #define IMR_RXFOVW BIT12 /* Receive FIFO Overflow */719 #define IMR_BcnInt_E BIT12750 #define RCR_ACF BIT12 /* Accept control type frame. Control frames BA, BAR, and PS-Poll (when …
56 #define DYNAMIC_BB_RXHP BIT12/* ODM_BB_RXHP */
22 #define BIT12 0x00001000 macro
31 #define BIT12 0x1000 macro
64 #define BIT12 0x00001000 macro
392 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */
377 ODM_BB_RXHP = BIT12,
665 PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); in odm_FalseAlarmCounterStatistics()
382 #define IRQ_TXIDLE BIT124186 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()4187 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4188 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4189 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4259 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()4260 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4261 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4262 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
370 #define RRSR_MCS0 BIT12
779 #define LPFC_SLI4_INTR12 BIT12
