Searched refs:APLL (Results 1 – 11 of 11) sorted by relevance
1 Binding for Texas Instruments APLL clock.6 register-mapped APLL with usually two selectable input clocks10 modes (locked, low power stop etc.) APLL mostly behaves like20 - reg : address and length of the register set for controlling the APLL.
43 <&clk APLL>,
27 #define APLL 18 macro
14 #define APLL 2 macro
22 #define APLL 11 macro
236 case APLL: in ma35d1_clk_pll_recalc_rate()268 case APLL: in ma35d1_clk_pll_round_rate()
506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", in ma35d1_clocks_probe()
295 .pll = DEF_PLL(APLL),
35 - 0 0 APLL
235 * Fix the emac parent clock is DPLL instead of APLL.
