1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34
35 #define pr_fmt(fmt) "amdgpu: " fmt
36
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40
41 #define dev_fmt(fmt) "amdgpu: " fmt
42
43 #include "amdgpu_ctx.h"
44
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53
54 #include <drm/ttm/ttm_bo.h>
55 #include <drm/ttm/ttm_placement.h>
56
57 #include <drm/amdgpu_drm.h>
58 #include <drm/drm_gem.h>
59 #include <drm/drm_ioctl.h>
60
61 #include <kgd_kfd_interface.h>
62 #include "dm_pp_interface.h"
63 #include "kgd_pp_interface.h"
64
65 #include "amd_shared.h"
66 #include "amdgpu_mode.h"
67 #include "amdgpu_ih.h"
68 #include "amdgpu_irq.h"
69 #include "amdgpu_ucode.h"
70 #include "amdgpu_ttm.h"
71 #include "amdgpu_psp.h"
72 #include "amdgpu_gds.h"
73 #include "amdgpu_sync.h"
74 #include "amdgpu_ring.h"
75 #include "amdgpu_vm.h"
76 #include "amdgpu_dpm.h"
77 #include "amdgpu_acp.h"
78 #include "amdgpu_uvd.h"
79 #include "amdgpu_vce.h"
80 #include "amdgpu_vcn.h"
81 #include "amdgpu_jpeg.h"
82 #include "amdgpu_gmc.h"
83 #include "amdgpu_gfx.h"
84 #include "amdgpu_sdma.h"
85 #include "amdgpu_lsdma.h"
86 #include "amdgpu_nbio.h"
87 #include "amdgpu_hdp.h"
88 #include "amdgpu_dm.h"
89 #include "amdgpu_virt.h"
90 #include "amdgpu_csa.h"
91 #include "amdgpu_mes_ctx.h"
92 #include "amdgpu_gart.h"
93 #include "amdgpu_debugfs.h"
94 #include "amdgpu_job.h"
95 #include "amdgpu_bo_list.h"
96 #include "amdgpu_gem.h"
97 #include "amdgpu_doorbell.h"
98 #include "amdgpu_amdkfd.h"
99 #include "amdgpu_discovery.h"
100 #include "amdgpu_mes.h"
101 #include "amdgpu_umc.h"
102 #include "amdgpu_mmhub.h"
103 #include "amdgpu_gfxhub.h"
104 #include "amdgpu_df.h"
105 #include "amdgpu_smuio.h"
106 #include "amdgpu_fdinfo.h"
107 #include "amdgpu_mca.h"
108 #include "amdgpu_ras.h"
109 #include "amdgpu_xcp.h"
110
111 #define MAX_GPU_INSTANCE 64
112
113 struct amdgpu_gpu_instance
114 {
115 struct amdgpu_device *adev;
116 int mgpu_fan_enabled;
117 };
118
119 struct amdgpu_mgpu_info
120 {
121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
122 struct mutex mutex;
123 uint32_t num_gpu;
124 uint32_t num_dgpu;
125 uint32_t num_apu;
126
127 /* delayed reset_func for XGMI configuration if necessary */
128 struct delayed_work delayed_reset_work;
129 bool pending_reset;
130 };
131
132 enum amdgpu_ss {
133 AMDGPU_SS_DRV_LOAD,
134 AMDGPU_SS_DEV_D0,
135 AMDGPU_SS_DEV_D3,
136 AMDGPU_SS_DRV_UNLOAD
137 };
138
139 struct amdgpu_watchdog_timer
140 {
141 bool timeout_fatal_disable;
142 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
143 };
144
145 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
146
147 /*
148 * Modules parameters.
149 */
150 extern int amdgpu_modeset;
151 extern unsigned int amdgpu_vram_limit;
152 extern int amdgpu_vis_vram_limit;
153 extern int amdgpu_gart_size;
154 extern int amdgpu_gtt_size;
155 extern int amdgpu_moverate;
156 extern int amdgpu_audio;
157 extern int amdgpu_disp_priority;
158 extern int amdgpu_hw_i2c;
159 extern int amdgpu_pcie_gen2;
160 extern int amdgpu_msi;
161 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
162 extern int amdgpu_dpm;
163 extern int amdgpu_fw_load_type;
164 extern int amdgpu_aspm;
165 extern int amdgpu_runtime_pm;
166 extern uint amdgpu_ip_block_mask;
167 extern int amdgpu_bapm;
168 extern int amdgpu_deep_color;
169 extern int amdgpu_vm_size;
170 extern int amdgpu_vm_block_size;
171 extern int amdgpu_vm_fragment_size;
172 extern int amdgpu_vm_fault_stop;
173 extern int amdgpu_vm_debug;
174 extern int amdgpu_vm_update_mode;
175 extern int amdgpu_exp_hw_support;
176 extern int amdgpu_dc;
177 extern int amdgpu_sched_jobs;
178 extern int amdgpu_sched_hw_submission;
179 extern uint amdgpu_pcie_gen_cap;
180 extern uint amdgpu_pcie_lane_cap;
181 extern u64 amdgpu_cg_mask;
182 extern uint amdgpu_pg_mask;
183 extern uint amdgpu_sdma_phase_quantum;
184 extern char *amdgpu_disable_cu;
185 extern char *amdgpu_virtual_display;
186 extern uint amdgpu_pp_feature_mask;
187 extern uint amdgpu_force_long_training;
188 extern int amdgpu_lbpw;
189 extern int amdgpu_compute_multipipe;
190 extern int amdgpu_gpu_recovery;
191 extern int amdgpu_emu_mode;
192 extern uint amdgpu_smu_memory_pool_size;
193 extern int amdgpu_smu_pptable_id;
194 extern uint amdgpu_dc_feature_mask;
195 extern uint amdgpu_dc_debug_mask;
196 extern uint amdgpu_dc_visual_confirm;
197 extern uint amdgpu_dm_abm_level;
198 extern int amdgpu_backlight;
199 extern struct amdgpu_mgpu_info mgpu_info;
200 extern int amdgpu_ras_enable;
201 extern uint amdgpu_ras_mask;
202 extern int amdgpu_bad_page_threshold;
203 extern bool amdgpu_ignore_bad_page_threshold;
204 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
205 extern int amdgpu_async_gfx_ring;
206 extern int amdgpu_mcbp;
207 extern int amdgpu_discovery;
208 extern int amdgpu_mes;
209 extern int amdgpu_mes_kiq;
210 extern int amdgpu_noretry;
211 extern int amdgpu_force_asic_type;
212 extern int amdgpu_smartshift_bias;
213 extern int amdgpu_use_xgmi_p2p;
214 extern int amdgpu_mtype_local;
215 extern bool enforce_isolation;
216 #ifdef CONFIG_HSA_AMD
217 extern int sched_policy;
218 extern bool debug_evictions;
219 extern bool no_system_mem_limit;
220 extern int halt_if_hws_hang;
221 #else
222 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
223 static const bool __maybe_unused debug_evictions; /* = false */
224 static const bool __maybe_unused no_system_mem_limit;
225 static const int __maybe_unused halt_if_hws_hang;
226 #endif
227 #ifdef CONFIG_HSA_AMD_P2P
228 extern bool pcie_p2p;
229 #endif
230
231 extern int amdgpu_tmz;
232 extern int amdgpu_reset_method;
233
234 #ifdef CONFIG_DRM_AMDGPU_SI
235 extern int amdgpu_si_support;
236 #endif
237 #ifdef CONFIG_DRM_AMDGPU_CIK
238 extern int amdgpu_cik_support;
239 #endif
240 extern int amdgpu_num_kcq;
241
242 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
243 extern int amdgpu_vcnfw_log;
244 extern int amdgpu_sg_display;
245
246 extern int amdgpu_user_partt_mode;
247
248 #define AMDGPU_VM_MAX_NUM_CTX 4096
249 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
250 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
251 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
252 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
253 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
254 #define AMDGPUFB_CONN_LIMIT 4
255 #define AMDGPU_BIOS_NUM_SCRATCH 16
256
257 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
258
259 /* hard reset data */
260 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
261
262 /* reset flags */
263 #define AMDGPU_RESET_GFX (1 << 0)
264 #define AMDGPU_RESET_COMPUTE (1 << 1)
265 #define AMDGPU_RESET_DMA (1 << 2)
266 #define AMDGPU_RESET_CP (1 << 3)
267 #define AMDGPU_RESET_GRBM (1 << 4)
268 #define AMDGPU_RESET_DMA1 (1 << 5)
269 #define AMDGPU_RESET_RLC (1 << 6)
270 #define AMDGPU_RESET_SEM (1 << 7)
271 #define AMDGPU_RESET_IH (1 << 8)
272 #define AMDGPU_RESET_VMC (1 << 9)
273 #define AMDGPU_RESET_MC (1 << 10)
274 #define AMDGPU_RESET_DISPLAY (1 << 11)
275 #define AMDGPU_RESET_UVD (1 << 12)
276 #define AMDGPU_RESET_VCE (1 << 13)
277 #define AMDGPU_RESET_VCE1 (1 << 14)
278
279 /* max cursor sizes (in pixels) */
280 #define CIK_CURSOR_WIDTH 128
281 #define CIK_CURSOR_HEIGHT 128
282
283 /* smart shift bias level limits */
284 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
285 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
286
287 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
288 #define AMDGPU_SWCTF_EXTRA_DELAY 50
289
290 struct amdgpu_xcp_mgr;
291 struct amdgpu_device;
292 struct amdgpu_irq_src;
293 struct amdgpu_fpriv;
294 struct amdgpu_bo_va_mapping;
295 struct kfd_vm_fault_info;
296 struct amdgpu_hive_info;
297 struct amdgpu_reset_context;
298 struct amdgpu_reset_control;
299
300 enum amdgpu_cp_irq {
301 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
302 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
303 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
304 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
305 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
306 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
307 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
308 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
309 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
310 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
311
312 AMDGPU_CP_IRQ_LAST
313 };
314
315 enum amdgpu_thermal_irq {
316 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
317 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
318
319 AMDGPU_THERMAL_IRQ_LAST
320 };
321
322 enum amdgpu_kiq_irq {
323 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
324 AMDGPU_CP_KIQ_IRQ_LAST
325 };
326 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
327 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
328 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
329 #define MAX_KIQ_REG_TRY 1000
330
331 int amdgpu_device_ip_set_clockgating_state(void *dev,
332 enum amd_ip_block_type block_type,
333 enum amd_clockgating_state state);
334 int amdgpu_device_ip_set_powergating_state(void *dev,
335 enum amd_ip_block_type block_type,
336 enum amd_powergating_state state);
337 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
338 u64 *flags);
339 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
340 enum amd_ip_block_type block_type);
341 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
342 enum amd_ip_block_type block_type);
343
344 #define AMDGPU_MAX_IP_NUM 16
345
346 struct amdgpu_ip_block_status {
347 bool valid;
348 bool sw;
349 bool hw;
350 bool late_initialized;
351 bool hang;
352 };
353
354 struct amdgpu_ip_block_version {
355 const enum amd_ip_block_type type;
356 const u32 major;
357 const u32 minor;
358 const u32 rev;
359 const struct amd_ip_funcs *funcs;
360 };
361
362 #define HW_REV(_Major, _Minor, _Rev) \
363 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
364
365 struct amdgpu_ip_block {
366 struct amdgpu_ip_block_status status;
367 const struct amdgpu_ip_block_version *version;
368 };
369
370 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
371 enum amd_ip_block_type type,
372 u32 major, u32 minor);
373
374 struct amdgpu_ip_block *
375 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
376 enum amd_ip_block_type type);
377
378 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
379 const struct amdgpu_ip_block_version *ip_block_version);
380
381 /*
382 * BIOS.
383 */
384 bool amdgpu_get_bios(struct amdgpu_device *adev);
385 bool amdgpu_read_bios(struct amdgpu_device *adev);
386 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
387 u8 *bios, u32 length_bytes);
388 /*
389 * Clocks
390 */
391
392 #define AMDGPU_MAX_PPLL 3
393
394 struct amdgpu_clock {
395 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
396 struct amdgpu_pll spll;
397 struct amdgpu_pll mpll;
398 /* 10 Khz units */
399 uint32_t default_mclk;
400 uint32_t default_sclk;
401 uint32_t default_dispclk;
402 uint32_t current_dispclk;
403 uint32_t dp_extclk;
404 uint32_t max_pixel_clock;
405 };
406
407 /* sub-allocation manager, it has to be protected by another lock.
408 * By conception this is an helper for other part of the driver
409 * like the indirect buffer or semaphore, which both have their
410 * locking.
411 *
412 * Principe is simple, we keep a list of sub allocation in offset
413 * order (first entry has offset == 0, last entry has the highest
414 * offset).
415 *
416 * When allocating new object we first check if there is room at
417 * the end total_size - (last_object_offset + last_object_size) >=
418 * alloc_size. If so we allocate new object there.
419 *
420 * When there is not enough room at the end, we start waiting for
421 * each sub object until we reach object_offset+object_size >=
422 * alloc_size, this object then become the sub object we return.
423 *
424 * Alignment can't be bigger than page size.
425 *
426 * Hole are not considered for allocation to keep things simple.
427 * Assumption is that there won't be hole (all object on same
428 * alignment).
429 */
430
431 struct amdgpu_sa_manager {
432 struct drm_suballoc_manager base;
433 struct amdgpu_bo *bo;
434 uint64_t gpu_addr;
435 void *cpu_ptr;
436 };
437
438 int amdgpu_fence_slab_init(void);
439 void amdgpu_fence_slab_fini(void);
440
441 /*
442 * IRQS.
443 */
444
445 struct amdgpu_flip_work {
446 struct delayed_work flip_work;
447 struct work_struct unpin_work;
448 struct amdgpu_device *adev;
449 int crtc_id;
450 u32 target_vblank;
451 uint64_t base;
452 struct drm_pending_vblank_event *event;
453 struct amdgpu_bo *old_abo;
454 unsigned shared_count;
455 struct dma_fence **shared;
456 struct dma_fence_cb cb;
457 bool async;
458 };
459
460
461 /*
462 * file private structure
463 */
464
465 struct amdgpu_fpriv {
466 struct amdgpu_vm vm;
467 struct amdgpu_bo_va *prt_va;
468 struct amdgpu_bo_va *csa_va;
469 struct mutex bo_list_lock;
470 struct idr bo_list_handles;
471 struct amdgpu_ctx_mgr ctx_mgr;
472 /** GPU partition selection */
473 uint32_t xcp_id;
474 };
475
476 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
477
478 /*
479 * Writeback
480 */
481 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
482
483 struct amdgpu_wb {
484 struct amdgpu_bo *wb_obj;
485 volatile uint32_t *wb;
486 uint64_t gpu_addr;
487 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
488 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
489 };
490
491 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
492 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
493
494 /*
495 * Benchmarking
496 */
497 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
498
499 /*
500 * ASIC specific register table accessible by UMD
501 */
502 struct amdgpu_allowed_register_entry {
503 uint32_t reg_offset;
504 bool grbm_indexed;
505 };
506
507 enum amd_reset_method {
508 AMD_RESET_METHOD_NONE = -1,
509 AMD_RESET_METHOD_LEGACY = 0,
510 AMD_RESET_METHOD_MODE0,
511 AMD_RESET_METHOD_MODE1,
512 AMD_RESET_METHOD_MODE2,
513 AMD_RESET_METHOD_BACO,
514 AMD_RESET_METHOD_PCI,
515 };
516
517 struct amdgpu_video_codec_info {
518 u32 codec_type;
519 u32 max_width;
520 u32 max_height;
521 u32 max_pixels_per_frame;
522 u32 max_level;
523 };
524
525 #define codec_info_build(type, width, height, level) \
526 .codec_type = type,\
527 .max_width = width,\
528 .max_height = height,\
529 .max_pixels_per_frame = height * width,\
530 .max_level = level,
531
532 struct amdgpu_video_codecs {
533 const u32 codec_count;
534 const struct amdgpu_video_codec_info *codec_array;
535 };
536
537 /*
538 * ASIC specific functions.
539 */
540 struct amdgpu_asic_funcs {
541 bool (*read_disabled_bios)(struct amdgpu_device *adev);
542 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
543 u8 *bios, u32 length_bytes);
544 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
545 u32 sh_num, u32 reg_offset, u32 *value);
546 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
547 int (*reset)(struct amdgpu_device *adev);
548 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
549 /* get the reference clock */
550 u32 (*get_xclk)(struct amdgpu_device *adev);
551 /* MM block clocks */
552 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
553 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
554 /* static power management */
555 int (*get_pcie_lanes)(struct amdgpu_device *adev);
556 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
557 /* get config memsize register */
558 u32 (*get_config_memsize)(struct amdgpu_device *adev);
559 /* flush hdp write queue */
560 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
561 /* invalidate hdp read cache */
562 void (*invalidate_hdp)(struct amdgpu_device *adev,
563 struct amdgpu_ring *ring);
564 /* check if the asic needs a full reset of if soft reset will work */
565 bool (*need_full_reset)(struct amdgpu_device *adev);
566 /* initialize doorbell layout for specific asic*/
567 void (*init_doorbell_index)(struct amdgpu_device *adev);
568 /* PCIe bandwidth usage */
569 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
570 uint64_t *count1);
571 /* do we need to reset the asic at init time (e.g., kexec) */
572 bool (*need_reset_on_init)(struct amdgpu_device *adev);
573 /* PCIe replay counter */
574 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
575 /* device supports BACO */
576 bool (*supports_baco)(struct amdgpu_device *adev);
577 /* pre asic_init quirks */
578 void (*pre_asic_init)(struct amdgpu_device *adev);
579 /* enter/exit umd stable pstate */
580 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
581 /* query video codecs */
582 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
583 const struct amdgpu_video_codecs **codecs);
584 /* encode "> 32bits" smn addressing */
585 u64 (*encode_ext_smn_addressing)(int ext_id);
586 };
587
588 /*
589 * IOCTL.
590 */
591 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
592 struct drm_file *filp);
593
594 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
595 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
596 struct drm_file *filp);
597 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
598 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
599 struct drm_file *filp);
600
601 /* VRAM scratch page for HDP bug, default vram page */
602 struct amdgpu_mem_scratch {
603 struct amdgpu_bo *robj;
604 volatile uint32_t *ptr;
605 u64 gpu_addr;
606 };
607
608 /*
609 * CGS
610 */
611 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
612 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
613
614 /*
615 * Core structure, functions and helpers.
616 */
617 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
618 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
619
620 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
621 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
622
623 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
624 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
625
626 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
627 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
628
629 struct amdgpu_mmio_remap {
630 u32 reg_offset;
631 resource_size_t bus_addr;
632 };
633
634 /* Define the HW IP blocks will be used in driver , add more if necessary */
635 enum amd_hw_ip_block_type {
636 GC_HWIP = 1,
637 HDP_HWIP,
638 SDMA0_HWIP,
639 SDMA1_HWIP,
640 SDMA2_HWIP,
641 SDMA3_HWIP,
642 SDMA4_HWIP,
643 SDMA5_HWIP,
644 SDMA6_HWIP,
645 SDMA7_HWIP,
646 LSDMA_HWIP,
647 MMHUB_HWIP,
648 ATHUB_HWIP,
649 NBIO_HWIP,
650 MP0_HWIP,
651 MP1_HWIP,
652 UVD_HWIP,
653 VCN_HWIP = UVD_HWIP,
654 JPEG_HWIP = VCN_HWIP,
655 VCN1_HWIP,
656 VCE_HWIP,
657 DF_HWIP,
658 DCE_HWIP,
659 OSSSYS_HWIP,
660 SMUIO_HWIP,
661 PWR_HWIP,
662 NBIF_HWIP,
663 THM_HWIP,
664 CLK_HWIP,
665 UMC_HWIP,
666 RSMU_HWIP,
667 XGMI_HWIP,
668 DCI_HWIP,
669 PCIE_HWIP,
670 MAX_HWIP
671 };
672
673 #define HWIP_MAX_INSTANCE 44
674
675 #define HW_ID_MAX 300
676 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
677 #define IP_VERSION_MAJ(ver) ((ver) >> 16)
678 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
679 #define IP_VERSION_REV(ver) ((ver) & 0xFF)
680
681 struct amdgpu_ip_map_info {
682 /* Map of logical to actual dev instances/mask */
683 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
684 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
685 enum amd_hw_ip_block_type block,
686 int8_t inst);
687 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
688 enum amd_hw_ip_block_type block,
689 uint32_t mask);
690 };
691
692 struct amd_powerplay {
693 void *pp_handle;
694 const struct amd_pm_funcs *pp_funcs;
695 };
696
697 struct ip_discovery_top;
698
699 /* polaris10 kickers */
700 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
701 ((rid == 0xE3) || \
702 (rid == 0xE4) || \
703 (rid == 0xE5) || \
704 (rid == 0xE7) || \
705 (rid == 0xEF))) || \
706 ((did == 0x6FDF) && \
707 ((rid == 0xE7) || \
708 (rid == 0xEF) || \
709 (rid == 0xFF))))
710
711 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
712 ((rid == 0xE1) || \
713 (rid == 0xF7)))
714
715 /* polaris11 kickers */
716 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
717 ((rid == 0xE0) || \
718 (rid == 0xE5))) || \
719 ((did == 0x67FF) && \
720 ((rid == 0xCF) || \
721 (rid == 0xEF) || \
722 (rid == 0xFF))))
723
724 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
725 ((rid == 0xE2)))
726
727 /* polaris12 kickers */
728 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
729 ((rid == 0xC0) || \
730 (rid == 0xC1) || \
731 (rid == 0xC3) || \
732 (rid == 0xC7))) || \
733 ((did == 0x6981) && \
734 ((rid == 0x00) || \
735 (rid == 0x01) || \
736 (rid == 0x10))))
737
738 struct amdgpu_mqd_prop {
739 uint64_t mqd_gpu_addr;
740 uint64_t hqd_base_gpu_addr;
741 uint64_t rptr_gpu_addr;
742 uint64_t wptr_gpu_addr;
743 uint32_t queue_size;
744 bool use_doorbell;
745 uint32_t doorbell_index;
746 uint64_t eop_gpu_addr;
747 uint32_t hqd_pipe_priority;
748 uint32_t hqd_queue_priority;
749 bool hqd_active;
750 };
751
752 struct amdgpu_mqd {
753 unsigned mqd_size;
754 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
755 struct amdgpu_mqd_prop *p);
756 };
757
758 #define AMDGPU_RESET_MAGIC_NUM 64
759 #define AMDGPU_MAX_DF_PERFMONS 4
760 #define AMDGPU_PRODUCT_NAME_LEN 64
761 struct amdgpu_reset_domain;
762
763 /*
764 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
765 */
766 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
767
768 struct amdgpu_device {
769 struct device *dev;
770 struct pci_dev *pdev;
771 struct drm_device ddev;
772
773 #ifdef CONFIG_DRM_AMD_ACP
774 struct amdgpu_acp acp;
775 #endif
776 struct amdgpu_hive_info *hive;
777 struct amdgpu_xcp_mgr *xcp_mgr;
778 /* ASIC */
779 enum amd_asic_type asic_type;
780 uint32_t family;
781 uint32_t rev_id;
782 uint32_t external_rev_id;
783 unsigned long flags;
784 unsigned long apu_flags;
785 int usec_timeout;
786 const struct amdgpu_asic_funcs *asic_funcs;
787 bool shutdown;
788 bool need_swiotlb;
789 bool accel_working;
790 struct notifier_block acpi_nb;
791 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
792 struct debugfs_blob_wrapper debugfs_vbios_blob;
793 struct debugfs_blob_wrapper debugfs_discovery_blob;
794 struct mutex srbm_mutex;
795 /* GRBM index mutex. Protects concurrent access to GRBM index */
796 struct mutex grbm_idx_mutex;
797 struct dev_pm_domain vga_pm_domain;
798 bool have_disp_power_ref;
799 bool have_atomics_support;
800
801 /* BIOS */
802 bool is_atom_fw;
803 uint8_t *bios;
804 uint32_t bios_size;
805 uint32_t bios_scratch_reg_offset;
806 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
807
808 /* Register/doorbell mmio */
809 resource_size_t rmmio_base;
810 resource_size_t rmmio_size;
811 void __iomem *rmmio;
812 /* protects concurrent MM_INDEX/DATA based register access */
813 spinlock_t mmio_idx_lock;
814 struct amdgpu_mmio_remap rmmio_remap;
815 /* protects concurrent SMC based register access */
816 spinlock_t smc_idx_lock;
817 amdgpu_rreg_t smc_rreg;
818 amdgpu_wreg_t smc_wreg;
819 /* protects concurrent PCIE register access */
820 spinlock_t pcie_idx_lock;
821 amdgpu_rreg_t pcie_rreg;
822 amdgpu_wreg_t pcie_wreg;
823 amdgpu_rreg_t pciep_rreg;
824 amdgpu_wreg_t pciep_wreg;
825 amdgpu_rreg_ext_t pcie_rreg_ext;
826 amdgpu_wreg_ext_t pcie_wreg_ext;
827 amdgpu_rreg64_t pcie_rreg64;
828 amdgpu_wreg64_t pcie_wreg64;
829 /* protects concurrent UVD register access */
830 spinlock_t uvd_ctx_idx_lock;
831 amdgpu_rreg_t uvd_ctx_rreg;
832 amdgpu_wreg_t uvd_ctx_wreg;
833 /* protects concurrent DIDT register access */
834 spinlock_t didt_idx_lock;
835 amdgpu_rreg_t didt_rreg;
836 amdgpu_wreg_t didt_wreg;
837 /* protects concurrent gc_cac register access */
838 spinlock_t gc_cac_idx_lock;
839 amdgpu_rreg_t gc_cac_rreg;
840 amdgpu_wreg_t gc_cac_wreg;
841 /* protects concurrent se_cac register access */
842 spinlock_t se_cac_idx_lock;
843 amdgpu_rreg_t se_cac_rreg;
844 amdgpu_wreg_t se_cac_wreg;
845 /* protects concurrent ENDPOINT (audio) register access */
846 spinlock_t audio_endpt_idx_lock;
847 amdgpu_block_rreg_t audio_endpt_rreg;
848 amdgpu_block_wreg_t audio_endpt_wreg;
849 struct amdgpu_doorbell doorbell;
850
851 /* clock/pll info */
852 struct amdgpu_clock clock;
853
854 /* MC */
855 struct amdgpu_gmc gmc;
856 struct amdgpu_gart gart;
857 dma_addr_t dummy_page_addr;
858 struct amdgpu_vm_manager vm_manager;
859 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
860 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
861
862 /* memory management */
863 struct amdgpu_mman mman;
864 struct amdgpu_mem_scratch mem_scratch;
865 struct amdgpu_wb wb;
866 atomic64_t num_bytes_moved;
867 atomic64_t num_evictions;
868 atomic64_t num_vram_cpu_page_faults;
869 atomic_t gpu_reset_counter;
870 atomic_t vram_lost_counter;
871
872 /* data for buffer migration throttling */
873 struct {
874 spinlock_t lock;
875 s64 last_update_us;
876 s64 accum_us; /* accumulated microseconds */
877 s64 accum_us_vis; /* for visible VRAM */
878 u32 log2_max_MBps;
879 } mm_stats;
880
881 /* display */
882 bool enable_virtual_display;
883 struct amdgpu_vkms_output *amdgpu_vkms_output;
884 struct amdgpu_mode_info mode_info;
885 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
886 struct delayed_work hotplug_work;
887 struct amdgpu_irq_src crtc_irq;
888 struct amdgpu_irq_src vline0_irq;
889 struct amdgpu_irq_src vupdate_irq;
890 struct amdgpu_irq_src pageflip_irq;
891 struct amdgpu_irq_src hpd_irq;
892 struct amdgpu_irq_src dmub_trace_irq;
893 struct amdgpu_irq_src dmub_outbox_irq;
894
895 /* rings */
896 u64 fence_context;
897 unsigned num_rings;
898 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
899 struct dma_fence __rcu *gang_submit;
900 bool ib_pool_ready;
901 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
902 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
903
904 /* interrupts */
905 struct amdgpu_irq irq;
906
907 /* powerplay */
908 struct amd_powerplay powerplay;
909 struct amdgpu_pm pm;
910 u64 cg_flags;
911 u32 pg_flags;
912
913 /* nbio */
914 struct amdgpu_nbio nbio;
915
916 /* hdp */
917 struct amdgpu_hdp hdp;
918
919 /* smuio */
920 struct amdgpu_smuio smuio;
921
922 /* mmhub */
923 struct amdgpu_mmhub mmhub;
924
925 /* gfxhub */
926 struct amdgpu_gfxhub gfxhub;
927
928 /* gfx */
929 struct amdgpu_gfx gfx;
930
931 /* sdma */
932 struct amdgpu_sdma sdma;
933
934 /* lsdma */
935 struct amdgpu_lsdma lsdma;
936
937 /* uvd */
938 struct amdgpu_uvd uvd;
939
940 /* vce */
941 struct amdgpu_vce vce;
942
943 /* vcn */
944 struct amdgpu_vcn vcn;
945
946 /* jpeg */
947 struct amdgpu_jpeg jpeg;
948
949 /* firmwares */
950 struct amdgpu_firmware firmware;
951
952 /* PSP */
953 struct psp_context psp;
954
955 /* GDS */
956 struct amdgpu_gds gds;
957
958 /* KFD */
959 struct amdgpu_kfd_dev kfd;
960
961 /* UMC */
962 struct amdgpu_umc umc;
963
964 /* display related functionality */
965 struct amdgpu_display_manager dm;
966
967 /* mes */
968 bool enable_mes;
969 bool enable_mes_kiq;
970 struct amdgpu_mes mes;
971 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
972
973 /* df */
974 struct amdgpu_df df;
975
976 /* MCA */
977 struct amdgpu_mca mca;
978
979 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
980 uint32_t harvest_ip_mask;
981 int num_ip_blocks;
982 struct mutex mn_lock;
983 DECLARE_HASHTABLE(mn_hash, 7);
984
985 /* tracking pinned memory */
986 atomic64_t vram_pin_size;
987 atomic64_t visible_pin_size;
988 atomic64_t gart_pin_size;
989
990 /* soc15 register offset based on ip, instance and segment */
991 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
992 struct amdgpu_ip_map_info ip_map;
993
994 /* delayed work_func for deferring clockgating during resume */
995 struct delayed_work delayed_init_work;
996
997 struct amdgpu_virt virt;
998
999 /* link all shadow bo */
1000 struct list_head shadow_list;
1001 struct mutex shadow_list_lock;
1002
1003 /* record hw reset is performed */
1004 bool has_hw_reset;
1005 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1006
1007 /* s3/s4 mask */
1008 bool in_suspend;
1009 bool in_s3;
1010 bool in_s4;
1011 bool in_s0ix;
1012
1013 enum pp_mp1_state mp1_state;
1014 struct amdgpu_doorbell_index doorbell_index;
1015
1016 struct mutex notifier_lock;
1017
1018 int asic_reset_res;
1019 struct work_struct xgmi_reset_work;
1020 struct list_head reset_list;
1021
1022 long gfx_timeout;
1023 long sdma_timeout;
1024 long video_timeout;
1025 long compute_timeout;
1026
1027 uint64_t unique_id;
1028 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1029
1030 /* enable runtime pm on the device */
1031 bool in_runpm;
1032 bool has_pr3;
1033
1034 bool ucode_sysfs_en;
1035
1036 /* Chip product information */
1037 char product_number[20];
1038 char product_name[AMDGPU_PRODUCT_NAME_LEN];
1039 char serial[20];
1040
1041 atomic_t throttling_logging_enabled;
1042 struct ratelimit_state throttling_logging_rs;
1043 uint32_t ras_hw_enabled;
1044 uint32_t ras_enabled;
1045
1046 bool no_hw_access;
1047 struct pci_saved_state *pci_state;
1048 pci_channel_state_t pci_channel_state;
1049
1050 /* Track auto wait count on s_barrier settings */
1051 bool barrier_has_auto_waitcnt;
1052
1053 struct amdgpu_reset_control *reset_cntl;
1054 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1055
1056 bool ram_is_direct_mapped;
1057
1058 struct list_head ras_list;
1059
1060 struct ip_discovery_top *ip_top;
1061
1062 struct amdgpu_reset_domain *reset_domain;
1063
1064 struct mutex benchmark_mutex;
1065
1066 /* reset dump register */
1067 uint32_t *reset_dump_reg_list;
1068 uint32_t *reset_dump_reg_value;
1069 int num_regs;
1070 #ifdef CONFIG_DEV_COREDUMP
1071 struct amdgpu_task_info reset_task_info;
1072 bool reset_vram_lost;
1073 struct timespec64 reset_time;
1074 #endif
1075
1076 bool scpm_enabled;
1077 uint32_t scpm_status;
1078
1079 struct work_struct reset_work;
1080
1081 bool job_hang;
1082 bool dc_enabled;
1083 /* Mask of active clusters */
1084 uint32_t aid_mask;
1085 };
1086
drm_to_adev(struct drm_device * ddev)1087 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1088 {
1089 return container_of(ddev, struct amdgpu_device, ddev);
1090 }
1091
adev_to_drm(struct amdgpu_device * adev)1092 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1093 {
1094 return &adev->ddev;
1095 }
1096
amdgpu_ttm_adev(struct ttm_device * bdev)1097 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1098 {
1099 return container_of(bdev, struct amdgpu_device, mman.bdev);
1100 }
1101
1102 int amdgpu_device_init(struct amdgpu_device *adev,
1103 uint32_t flags);
1104 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1105 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1106
1107 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1108
1109 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1110 void *buf, size_t size, bool write);
1111 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1112 void *buf, size_t size, bool write);
1113
1114 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1115 void *buf, size_t size, bool write);
1116 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1117 uint32_t inst, uint32_t reg_addr, char reg_name[],
1118 uint32_t expected_value, uint32_t mask);
1119 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1120 uint32_t reg, uint32_t acc_flags);
1121 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1122 u64 reg_addr);
1123 void amdgpu_device_wreg(struct amdgpu_device *adev,
1124 uint32_t reg, uint32_t v,
1125 uint32_t acc_flags);
1126 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1127 u64 reg_addr, u32 reg_data);
1128 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1129 uint32_t reg, uint32_t v, uint32_t xcc_id);
1130 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1131 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1132
1133 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1134 u32 reg_addr);
1135 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1136 u32 reg_addr);
1137 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1138 u32 reg_addr, u32 reg_data);
1139 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1140 u32 reg_addr, u64 reg_data);
1141 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1142 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1143 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1144
1145 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1146
1147 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1148 struct amdgpu_reset_context *reset_context);
1149
1150 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1151 struct amdgpu_reset_context *reset_context);
1152
1153 int emu_soc_asic_init(struct amdgpu_device *adev);
1154
1155 /*
1156 * Registers read & write functions.
1157 */
1158 #define AMDGPU_REGS_NO_KIQ (1<<1)
1159 #define AMDGPU_REGS_RLC (1<<2)
1160
1161 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1162 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1163
1164 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1165 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1166
1167 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1168 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1169
1170 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1171 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1172 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1173 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1174 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1175 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1176 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1177 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1178 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1179 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1180 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1181 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1182 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1183 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1184 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1185 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1186 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1187 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1188 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1189 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1190 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1191 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1192 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1193 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1194 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1195 #define WREG32_P(reg, val, mask) \
1196 do { \
1197 uint32_t tmp_ = RREG32(reg); \
1198 tmp_ &= (mask); \
1199 tmp_ |= ((val) & ~(mask)); \
1200 WREG32(reg, tmp_); \
1201 } while (0)
1202 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1203 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1204 #define WREG32_PLL_P(reg, val, mask) \
1205 do { \
1206 uint32_t tmp_ = RREG32_PLL(reg); \
1207 tmp_ &= (mask); \
1208 tmp_ |= ((val) & ~(mask)); \
1209 WREG32_PLL(reg, tmp_); \
1210 } while (0)
1211
1212 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1213 do { \
1214 u32 tmp = RREG32_SMC(_Reg); \
1215 tmp &= (_Mask); \
1216 tmp |= ((_Val) & ~(_Mask)); \
1217 WREG32_SMC(_Reg, tmp); \
1218 } while (0)
1219
1220 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1221
1222 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1223 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1224
1225 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1226 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1227 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1228
1229 #define REG_GET_FIELD(value, reg, field) \
1230 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1231
1232 #define WREG32_FIELD(reg, field, val) \
1233 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1234
1235 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1236 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1237
1238 /*
1239 * BIOS helpers.
1240 */
1241 #define RBIOS8(i) (adev->bios[i])
1242 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1243 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1244
1245 /*
1246 * ASICs macro.
1247 */
1248 #define amdgpu_asic_set_vga_state(adev, state) \
1249 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1250 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1251 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1252 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1253 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1254 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1255 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1256 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1257 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1258 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1259 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1260 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1261 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1262 #define amdgpu_asic_flush_hdp(adev, r) \
1263 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1264 #define amdgpu_asic_invalidate_hdp(adev, r) \
1265 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1266 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1267 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1268 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1269 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1270 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1271 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1272 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1273 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1274 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1275 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1276 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1277
1278 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1279
1280 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1281 #define for_each_inst(i, inst_mask) \
1282 for (i = ffs(inst_mask); i-- != 0; \
1283 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1284
1285 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1286
1287 /* Common functions */
1288 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1289 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1290 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1291 struct amdgpu_job *job,
1292 struct amdgpu_reset_context *reset_context);
1293 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1294 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1295 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1296 bool amdgpu_device_pcie_dynamic_switching_supported(void);
1297 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1298 bool amdgpu_device_aspm_support_quirk(void);
1299
1300 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1301 u64 num_vis_bytes);
1302 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1303 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1304 const u32 *registers,
1305 const u32 array_size);
1306
1307 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1308 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1309 bool amdgpu_device_supports_px(struct drm_device *dev);
1310 bool amdgpu_device_supports_boco(struct drm_device *dev);
1311 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1312 bool amdgpu_device_supports_baco(struct drm_device *dev);
1313 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1314 struct amdgpu_device *peer_adev);
1315 int amdgpu_device_baco_enter(struct drm_device *dev);
1316 int amdgpu_device_baco_exit(struct drm_device *dev);
1317
1318 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1319 struct amdgpu_ring *ring);
1320 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1321 struct amdgpu_ring *ring);
1322
1323 void amdgpu_device_halt(struct amdgpu_device *adev);
1324 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1325 u32 reg);
1326 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1327 u32 reg, u32 v);
1328 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1329 struct dma_fence *gang);
1330 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1331
1332 /* atpx handler */
1333 #if defined(CONFIG_VGA_SWITCHEROO)
1334 void amdgpu_register_atpx_handler(void);
1335 void amdgpu_unregister_atpx_handler(void);
1336 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1337 bool amdgpu_is_atpx_hybrid(void);
1338 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1339 bool amdgpu_has_atpx(void);
1340 #else
amdgpu_register_atpx_handler(void)1341 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)1342 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1343 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)1344 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1345 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1346 static inline bool amdgpu_has_atpx(void) { return false; }
1347 #endif
1348
1349 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1350 void *amdgpu_atpx_get_dhandle(void);
1351 #else
amdgpu_atpx_get_dhandle(void)1352 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1353 #endif
1354
1355 /*
1356 * KMS
1357 */
1358 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1359 extern const int amdgpu_max_kms_ioctl;
1360
1361 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1362 void amdgpu_driver_unload_kms(struct drm_device *dev);
1363 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1364 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1365 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1366 struct drm_file *file_priv);
1367 void amdgpu_driver_release_kms(struct drm_device *dev);
1368
1369 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1370 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1371 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1372 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1373 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1374 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1375 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1376 struct drm_file *filp);
1377
1378 /*
1379 * functions used by amdgpu_encoder.c
1380 */
1381 struct amdgpu_afmt_acr {
1382 u32 clock;
1383
1384 int n_32khz;
1385 int cts_32khz;
1386
1387 int n_44_1khz;
1388 int cts_44_1khz;
1389
1390 int n_48khz;
1391 int cts_48khz;
1392
1393 };
1394
1395 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1396
1397 /* amdgpu_acpi.c */
1398
1399 struct amdgpu_numa_info {
1400 uint64_t size;
1401 int pxm;
1402 int nid;
1403 };
1404
1405 /* ATCS Device/Driver State */
1406 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1407 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1408 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1409 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1410
1411 #if defined(CONFIG_ACPI)
1412 int amdgpu_acpi_init(struct amdgpu_device *adev);
1413 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1414 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1415 bool amdgpu_acpi_is_power_shift_control_supported(void);
1416 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1417 u8 perf_req, bool advertise);
1418 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1419 u8 dev_state, bool drv_state);
1420 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1421 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1422 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1423 u64 *tmr_size);
1424 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1425 struct amdgpu_numa_info *numa_info);
1426
1427 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1428 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1429 void amdgpu_acpi_detect(void);
1430 void amdgpu_acpi_release(void);
1431 #else
amdgpu_acpi_init(struct amdgpu_device * adev)1432 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_get_tmr_info(struct amdgpu_device * adev,u64 * tmr_offset,u64 * tmr_size)1433 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1434 u64 *tmr_offset, u64 *tmr_size)
1435 {
1436 return -EINVAL;
1437 }
amdgpu_acpi_get_mem_info(struct amdgpu_device * adev,int xcc_id,struct amdgpu_numa_info * numa_info)1438 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1439 int xcc_id,
1440 struct amdgpu_numa_info *numa_info)
1441 {
1442 return -EINVAL;
1443 }
amdgpu_acpi_fini(struct amdgpu_device * adev)1444 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
amdgpu_acpi_should_gpu_reset(struct amdgpu_device * adev)1445 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_detect(void)1446 static inline void amdgpu_acpi_detect(void) { }
amdgpu_acpi_release(void)1447 static inline void amdgpu_acpi_release(void) { }
amdgpu_acpi_is_power_shift_control_supported(void)1448 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
amdgpu_acpi_power_shift_control(struct amdgpu_device * adev,u8 dev_state,bool drv_state)1449 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1450 u8 dev_state, bool drv_state) { return 0; }
amdgpu_acpi_smart_shift_update(struct drm_device * dev,enum amdgpu_ss ss_state)1451 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1452 enum amdgpu_ss ss_state) { return 0; }
1453 #endif
1454
1455 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1456 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1457 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1458 #else
amdgpu_acpi_is_s0ix_active(struct amdgpu_device * adev)1459 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_is_s3_active(struct amdgpu_device * adev)1460 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1461 #endif
1462
1463 #if defined(CONFIG_DRM_AMD_DC)
1464 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1465 #else
amdgpu_dm_display_resume(struct amdgpu_device * adev)1466 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1467 #endif
1468
1469
1470 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1471 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1472
1473 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1474 pci_channel_state_t state);
1475 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1476 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1477 void amdgpu_pci_resume(struct pci_dev *pdev);
1478
1479 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1480 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1481
1482 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1483
1484 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1485 enum amd_clockgating_state state);
1486 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1487 enum amd_powergating_state state);
1488
amdgpu_device_has_timeouts_enabled(struct amdgpu_device * adev)1489 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1490 {
1491 return amdgpu_gpu_recovery != 0 &&
1492 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1493 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1494 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1495 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1496 }
1497
1498 #include "amdgpu_object.h"
1499
amdgpu_is_tmz(struct amdgpu_device * adev)1500 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1501 {
1502 return adev->gmc.tmz_enabled;
1503 }
1504
1505 int amdgpu_in_reset(struct amdgpu_device *adev);
1506
1507 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1508 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1509 extern const struct attribute_group amdgpu_flash_attr_group;
1510
1511 #endif
1512
