1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Analog Devices AD7768-1 SPI ADC driver
4 *
5 * Copyright 2017 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/sysfs.h>
17 #include <linux/spi/spi.h>
18
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/triggered_buffer.h>
24 #include <linux/iio/trigger_consumer.h>
25
26 /* AD7768 registers definition */
27 #define AD7768_REG_CHIP_TYPE 0x3
28 #define AD7768_REG_PROD_ID_L 0x4
29 #define AD7768_REG_PROD_ID_H 0x5
30 #define AD7768_REG_CHIP_GRADE 0x6
31 #define AD7768_REG_SCRATCH_PAD 0x0A
32 #define AD7768_REG_VENDOR_L 0x0C
33 #define AD7768_REG_VENDOR_H 0x0D
34 #define AD7768_REG_INTERFACE_FORMAT 0x14
35 #define AD7768_REG_POWER_CLOCK 0x15
36 #define AD7768_REG_ANALOG 0x16
37 #define AD7768_REG_ANALOG2 0x17
38 #define AD7768_REG_CONVERSION 0x18
39 #define AD7768_REG_DIGITAL_FILTER 0x19
40 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A
41 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B
42 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
43 #define AD7768_REG_SYNC_RESET 0x1D
44 #define AD7768_REG_GPIO_CONTROL 0x1E
45 #define AD7768_REG_GPIO_WRITE 0x1F
46 #define AD7768_REG_GPIO_READ 0x20
47 #define AD7768_REG_OFFSET_HI 0x21
48 #define AD7768_REG_OFFSET_MID 0x22
49 #define AD7768_REG_OFFSET_LO 0x23
50 #define AD7768_REG_GAIN_HI 0x24
51 #define AD7768_REG_GAIN_MID 0x25
52 #define AD7768_REG_GAIN_LO 0x26
53 #define AD7768_REG_SPI_DIAG_ENABLE 0x28
54 #define AD7768_REG_ADC_DIAG_ENABLE 0x29
55 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A
56 #define AD7768_REG_ADC_DATA 0x2C
57 #define AD7768_REG_MASTER_STATUS 0x2D
58 #define AD7768_REG_SPI_DIAG_STATUS 0x2E
59 #define AD7768_REG_ADC_DIAG_STATUS 0x2F
60 #define AD7768_REG_DIG_DIAG_STATUS 0x30
61 #define AD7768_REG_MCLK_COUNTER 0x31
62
63 /* AD7768_REG_POWER_CLOCK */
64 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
65 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
66 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
67 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
68
69 /* AD7768_REG_DIGITAL_FILTER */
70 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
71 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
72 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
73 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
74
75 /* AD7768_REG_CONVERSION */
76 #define AD7768_CONV_MODE_MSK GENMASK(2, 0)
77 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
78
79 #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F))
80 #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F)
81
82 enum ad7768_conv_mode {
83 AD7768_CONTINUOUS,
84 AD7768_ONE_SHOT,
85 AD7768_SINGLE,
86 AD7768_PERIODIC,
87 AD7768_STANDBY
88 };
89
90 enum ad7768_pwrmode {
91 AD7768_ECO_MODE = 0,
92 AD7768_MED_MODE = 2,
93 AD7768_FAST_MODE = 3
94 };
95
96 enum ad7768_mclk_div {
97 AD7768_MCLK_DIV_16,
98 AD7768_MCLK_DIV_8,
99 AD7768_MCLK_DIV_4,
100 AD7768_MCLK_DIV_2
101 };
102
103 enum ad7768_dec_rate {
104 AD7768_DEC_RATE_32 = 0,
105 AD7768_DEC_RATE_64 = 1,
106 AD7768_DEC_RATE_128 = 2,
107 AD7768_DEC_RATE_256 = 3,
108 AD7768_DEC_RATE_512 = 4,
109 AD7768_DEC_RATE_1024 = 5,
110 AD7768_DEC_RATE_8 = 9,
111 AD7768_DEC_RATE_16 = 10
112 };
113
114 struct ad7768_clk_configuration {
115 enum ad7768_mclk_div mclk_div;
116 enum ad7768_dec_rate dec_rate;
117 unsigned int clk_div;
118 enum ad7768_pwrmode pwrmode;
119 };
120
121 static const struct ad7768_clk_configuration ad7768_clk_config[] = {
122 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
123 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
124 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
125 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
126 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
127 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
128 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
129 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
130 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
131 { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
132 { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
133 };
134
135 static const struct iio_chan_spec ad7768_channels[] = {
136 {
137 .type = IIO_VOLTAGE,
138 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
139 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
140 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
141 .indexed = 1,
142 .channel = 0,
143 .scan_index = 0,
144 .scan_type = {
145 .sign = 'u',
146 .realbits = 24,
147 .storagebits = 32,
148 .shift = 8,
149 .endianness = IIO_BE,
150 },
151 },
152 };
153
154 struct ad7768_state {
155 struct spi_device *spi;
156 struct regulator *vref;
157 struct mutex lock;
158 struct clk *mclk;
159 unsigned int mclk_freq;
160 unsigned int samp_freq;
161 struct completion completion;
162 struct iio_trigger *trig;
163 struct gpio_desc *gpio_sync_in;
164 const char *labels[ARRAY_SIZE(ad7768_channels)];
165 /*
166 * DMA (thus cache coherency maintenance) may require the
167 * transfer buffers to live in their own cache lines.
168 */
169 union {
170 struct {
171 __be32 chan;
172 s64 timestamp;
173 } scan;
174 __be32 d32;
175 u8 d8[2];
176 } data __aligned(IIO_DMA_MINALIGN);
177 };
178
ad7768_spi_reg_read(struct ad7768_state * st,unsigned int addr,unsigned int len)179 static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
180 unsigned int len)
181 {
182 unsigned int shift;
183 int ret;
184
185 shift = 32 - (8 * len);
186 st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
187
188 ret = spi_write_then_read(st->spi, st->data.d8, 1,
189 &st->data.d32, len);
190 if (ret < 0)
191 return ret;
192
193 return (be32_to_cpu(st->data.d32) >> shift);
194 }
195
ad7768_spi_reg_write(struct ad7768_state * st,unsigned int addr,unsigned int val)196 static int ad7768_spi_reg_write(struct ad7768_state *st,
197 unsigned int addr,
198 unsigned int val)
199 {
200 st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
201 st->data.d8[1] = val & 0xFF;
202
203 return spi_write(st->spi, st->data.d8, 2);
204 }
205
ad7768_set_mode(struct ad7768_state * st,enum ad7768_conv_mode mode)206 static int ad7768_set_mode(struct ad7768_state *st,
207 enum ad7768_conv_mode mode)
208 {
209 int regval;
210
211 regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
212 if (regval < 0)
213 return regval;
214
215 regval &= ~AD7768_CONV_MODE_MSK;
216 regval |= AD7768_CONV_MODE(mode);
217
218 return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
219 }
220
ad7768_scan_direct(struct iio_dev * indio_dev)221 static int ad7768_scan_direct(struct iio_dev *indio_dev)
222 {
223 struct ad7768_state *st = iio_priv(indio_dev);
224 int readval, ret;
225
226 reinit_completion(&st->completion);
227
228 ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
229 if (ret < 0)
230 return ret;
231
232 ret = wait_for_completion_timeout(&st->completion,
233 msecs_to_jiffies(1000));
234 if (!ret)
235 return -ETIMEDOUT;
236
237 readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
238 if (readval < 0)
239 return readval;
240 /*
241 * Any SPI configuration of the AD7768-1 can only be
242 * performed in continuous conversion mode.
243 */
244 ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
245 if (ret < 0)
246 return ret;
247
248 return readval;
249 }
250
ad7768_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)251 static int ad7768_reg_access(struct iio_dev *indio_dev,
252 unsigned int reg,
253 unsigned int writeval,
254 unsigned int *readval)
255 {
256 struct ad7768_state *st = iio_priv(indio_dev);
257 int ret;
258
259 mutex_lock(&st->lock);
260 if (readval) {
261 ret = ad7768_spi_reg_read(st, reg, 1);
262 if (ret < 0)
263 goto err_unlock;
264 *readval = ret;
265 ret = 0;
266 } else {
267 ret = ad7768_spi_reg_write(st, reg, writeval);
268 }
269 err_unlock:
270 mutex_unlock(&st->lock);
271
272 return ret;
273 }
274
ad7768_set_dig_fil(struct ad7768_state * st,enum ad7768_dec_rate dec_rate)275 static int ad7768_set_dig_fil(struct ad7768_state *st,
276 enum ad7768_dec_rate dec_rate)
277 {
278 unsigned int mode;
279 int ret;
280
281 if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
282 mode = AD7768_DIG_FIL_FIL(dec_rate);
283 else
284 mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
285
286 ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
287 if (ret < 0)
288 return ret;
289
290 /* A sync-in pulse is required every time the filter dec rate changes */
291 gpiod_set_value(st->gpio_sync_in, 1);
292 gpiod_set_value(st->gpio_sync_in, 0);
293
294 return 0;
295 }
296
ad7768_set_freq(struct ad7768_state * st,unsigned int freq)297 static int ad7768_set_freq(struct ad7768_state *st,
298 unsigned int freq)
299 {
300 unsigned int diff_new, diff_old, pwr_mode, i, idx;
301 int res, ret;
302
303 diff_old = U32_MAX;
304 idx = 0;
305
306 res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
307
308 /* Find the closest match for the desired sampling frequency */
309 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
310 diff_new = abs(res - ad7768_clk_config[i].clk_div);
311 if (diff_new < diff_old) {
312 diff_old = diff_new;
313 idx = i;
314 }
315 }
316
317 /*
318 * Set both the mclk_div and pwrmode with a single write to the
319 * POWER_CLOCK register
320 */
321 pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
322 AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
323 ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
324 if (ret < 0)
325 return ret;
326
327 ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
328 if (ret < 0)
329 return ret;
330
331 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
332 ad7768_clk_config[idx].clk_div);
333
334 return 0;
335 }
336
ad7768_sampling_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)337 static ssize_t ad7768_sampling_freq_avail(struct device *dev,
338 struct device_attribute *attr,
339 char *buf)
340 {
341 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
342 struct ad7768_state *st = iio_priv(indio_dev);
343 unsigned int freq;
344 int i, len = 0;
345
346 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
347 freq = DIV_ROUND_CLOSEST(st->mclk_freq,
348 ad7768_clk_config[i].clk_div);
349 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
350 }
351
352 buf[len - 1] = '\n';
353
354 return len;
355 }
356
357 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
358
ad7768_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)359 static int ad7768_read_raw(struct iio_dev *indio_dev,
360 struct iio_chan_spec const *chan,
361 int *val, int *val2, long info)
362 {
363 struct ad7768_state *st = iio_priv(indio_dev);
364 int scale_uv, ret;
365
366 switch (info) {
367 case IIO_CHAN_INFO_RAW:
368 ret = iio_device_claim_direct_mode(indio_dev);
369 if (ret)
370 return ret;
371
372 ret = ad7768_scan_direct(indio_dev);
373 if (ret >= 0)
374 *val = ret;
375
376 iio_device_release_direct_mode(indio_dev);
377 if (ret < 0)
378 return ret;
379
380 return IIO_VAL_INT;
381
382 case IIO_CHAN_INFO_SCALE:
383 scale_uv = regulator_get_voltage(st->vref);
384 if (scale_uv < 0)
385 return scale_uv;
386
387 *val = (scale_uv * 2) / 1000;
388 *val2 = chan->scan_type.realbits;
389
390 return IIO_VAL_FRACTIONAL_LOG2;
391
392 case IIO_CHAN_INFO_SAMP_FREQ:
393 *val = st->samp_freq;
394
395 return IIO_VAL_INT;
396 }
397
398 return -EINVAL;
399 }
400
ad7768_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)401 static int ad7768_write_raw(struct iio_dev *indio_dev,
402 struct iio_chan_spec const *chan,
403 int val, int val2, long info)
404 {
405 struct ad7768_state *st = iio_priv(indio_dev);
406
407 switch (info) {
408 case IIO_CHAN_INFO_SAMP_FREQ:
409 return ad7768_set_freq(st, val);
410 default:
411 return -EINVAL;
412 }
413 }
414
ad7768_read_label(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,char * label)415 static int ad7768_read_label(struct iio_dev *indio_dev,
416 const struct iio_chan_spec *chan, char *label)
417 {
418 struct ad7768_state *st = iio_priv(indio_dev);
419
420 return sprintf(label, "%s\n", st->labels[chan->channel]);
421 }
422
423 static struct attribute *ad7768_attributes[] = {
424 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
425 NULL
426 };
427
428 static const struct attribute_group ad7768_group = {
429 .attrs = ad7768_attributes,
430 };
431
432 static const struct iio_info ad7768_info = {
433 .attrs = &ad7768_group,
434 .read_raw = &ad7768_read_raw,
435 .write_raw = &ad7768_write_raw,
436 .read_label = ad7768_read_label,
437 .debugfs_reg_access = &ad7768_reg_access,
438 };
439
ad7768_setup(struct ad7768_state * st)440 static int ad7768_setup(struct ad7768_state *st)
441 {
442 int ret;
443
444 /*
445 * Two writes to the SPI_RESET[1:0] bits are required to initiate
446 * a software reset. The bits must first be set to 11, and then
447 * to 10. When the sequence is detected, the reset occurs.
448 * See the datasheet, page 70.
449 */
450 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
451 if (ret)
452 return ret;
453
454 ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
455 if (ret)
456 return ret;
457
458 st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
459 GPIOD_OUT_LOW);
460 if (IS_ERR(st->gpio_sync_in))
461 return PTR_ERR(st->gpio_sync_in);
462
463 /* Set the default sampling frequency to 32000 kSPS */
464 return ad7768_set_freq(st, 32000);
465 }
466
ad7768_trigger_handler(int irq,void * p)467 static irqreturn_t ad7768_trigger_handler(int irq, void *p)
468 {
469 struct iio_poll_func *pf = p;
470 struct iio_dev *indio_dev = pf->indio_dev;
471 struct ad7768_state *st = iio_priv(indio_dev);
472 int ret;
473
474 mutex_lock(&st->lock);
475
476 ret = spi_read(st->spi, &st->data.scan.chan, 3);
477 if (ret < 0)
478 goto err_unlock;
479
480 iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
481 iio_get_time_ns(indio_dev));
482
483 err_unlock:
484 iio_trigger_notify_done(indio_dev->trig);
485 mutex_unlock(&st->lock);
486
487 return IRQ_HANDLED;
488 }
489
ad7768_interrupt(int irq,void * dev_id)490 static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
491 {
492 struct iio_dev *indio_dev = dev_id;
493 struct ad7768_state *st = iio_priv(indio_dev);
494
495 if (iio_buffer_enabled(indio_dev))
496 iio_trigger_poll(st->trig);
497 else
498 complete(&st->completion);
499
500 return IRQ_HANDLED;
501 };
502
ad7768_buffer_postenable(struct iio_dev * indio_dev)503 static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
504 {
505 struct ad7768_state *st = iio_priv(indio_dev);
506
507 /*
508 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
509 * continuous read mode. Subsequent data reads do not require an
510 * initial 8-bit write to query the ADC_DATA register.
511 */
512 return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
513 }
514
ad7768_buffer_predisable(struct iio_dev * indio_dev)515 static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
516 {
517 struct ad7768_state *st = iio_priv(indio_dev);
518
519 /*
520 * To exit continuous read mode, perform a single read of the ADC_DATA
521 * reg (0x2C), which allows further configuration of the device.
522 */
523 return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
524 }
525
526 static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
527 .postenable = &ad7768_buffer_postenable,
528 .predisable = &ad7768_buffer_predisable,
529 };
530
531 static const struct iio_trigger_ops ad7768_trigger_ops = {
532 .validate_device = iio_trigger_validate_own_device,
533 };
534
ad7768_regulator_disable(void * data)535 static void ad7768_regulator_disable(void *data)
536 {
537 struct ad7768_state *st = data;
538
539 regulator_disable(st->vref);
540 }
541
ad7768_set_channel_label(struct iio_dev * indio_dev,int num_channels)542 static int ad7768_set_channel_label(struct iio_dev *indio_dev,
543 int num_channels)
544 {
545 struct ad7768_state *st = iio_priv(indio_dev);
546 struct device *device = indio_dev->dev.parent;
547 struct fwnode_handle *fwnode;
548 struct fwnode_handle *child;
549 const char *label;
550 int crt_ch = 0;
551
552 fwnode = dev_fwnode(device);
553 fwnode_for_each_child_node(fwnode, child) {
554 if (fwnode_property_read_u32(child, "reg", &crt_ch))
555 continue;
556
557 if (crt_ch >= num_channels)
558 continue;
559
560 if (fwnode_property_read_string(child, "label", &label))
561 continue;
562
563 st->labels[crt_ch] = label;
564 }
565
566 return 0;
567 }
568
ad7768_probe(struct spi_device * spi)569 static int ad7768_probe(struct spi_device *spi)
570 {
571 struct ad7768_state *st;
572 struct iio_dev *indio_dev;
573 int ret;
574
575 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
576 if (!indio_dev)
577 return -ENOMEM;
578
579 st = iio_priv(indio_dev);
580 st->spi = spi;
581
582 st->vref = devm_regulator_get(&spi->dev, "vref");
583 if (IS_ERR(st->vref))
584 return PTR_ERR(st->vref);
585
586 ret = regulator_enable(st->vref);
587 if (ret) {
588 dev_err(&spi->dev, "Failed to enable specified vref supply\n");
589 return ret;
590 }
591
592 ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
593 if (ret)
594 return ret;
595
596 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
597 if (IS_ERR(st->mclk))
598 return PTR_ERR(st->mclk);
599
600 st->mclk_freq = clk_get_rate(st->mclk);
601
602 mutex_init(&st->lock);
603
604 indio_dev->channels = ad7768_channels;
605 indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
606 indio_dev->name = spi_get_device_id(spi)->name;
607 indio_dev->info = &ad7768_info;
608 indio_dev->modes = INDIO_DIRECT_MODE;
609
610 ret = ad7768_setup(st);
611 if (ret < 0) {
612 dev_err(&spi->dev, "AD7768 setup failed\n");
613 return ret;
614 }
615
616 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
617 indio_dev->name,
618 iio_device_id(indio_dev));
619 if (!st->trig)
620 return -ENOMEM;
621
622 st->trig->ops = &ad7768_trigger_ops;
623 iio_trigger_set_drvdata(st->trig, indio_dev);
624 ret = devm_iio_trigger_register(&spi->dev, st->trig);
625 if (ret)
626 return ret;
627
628 indio_dev->trig = iio_trigger_get(st->trig);
629
630 init_completion(&st->completion);
631
632 ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels));
633 if (ret)
634 return ret;
635
636 ret = devm_request_irq(&spi->dev, spi->irq,
637 &ad7768_interrupt,
638 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
639 indio_dev->name, indio_dev);
640 if (ret)
641 return ret;
642
643 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
644 &iio_pollfunc_store_time,
645 &ad7768_trigger_handler,
646 &ad7768_buffer_ops);
647 if (ret)
648 return ret;
649
650 return devm_iio_device_register(&spi->dev, indio_dev);
651 }
652
653 static const struct spi_device_id ad7768_id_table[] = {
654 { "ad7768-1", 0 },
655 {}
656 };
657 MODULE_DEVICE_TABLE(spi, ad7768_id_table);
658
659 static const struct of_device_id ad7768_of_match[] = {
660 { .compatible = "adi,ad7768-1" },
661 { },
662 };
663 MODULE_DEVICE_TABLE(of, ad7768_of_match);
664
665 static struct spi_driver ad7768_driver = {
666 .driver = {
667 .name = "ad7768-1",
668 .of_match_table = ad7768_of_match,
669 },
670 .probe = ad7768_probe,
671 .id_table = ad7768_id_table,
672 };
673 module_spi_driver(ad7768_driver);
674
675 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
676 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
677 MODULE_LICENSE("GPL v2");
678
