1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19 #include <linux/of.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/adc/ad_sigma_delta.h>
28
29 /* Registers */
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
38 /* (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
41
42 /* Communications Register Bit Designations (AD7192_REG_COMM) */
43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
44 #define AD7192_COMM_WRITE 0 /* Write Operation */
45 #define AD7192_COMM_READ BIT(6) /* Read Operation */
46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
48
49 /* Status Register Bit Designations (AD7192_REG_STAT) */
50 #define AD7192_STAT_RDY BIT(7) /* Ready */
51 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
52 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
53 #define AD7192_STAT_PARITY BIT(4) /* Parity */
54 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
57
58 /* Mode Register Bit Designations (AD7192_REG_MODE) */
59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
61 #define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */
62 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
68 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
69 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
70
71 /* Mode Register: AD7192_MODE_SEL options */
72 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
74 #define AD7192_MODE_IDLE 2 /* Idle Mode */
75 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
76 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
77 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
78 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
80
81 /* Mode Register: AD7192_MODE_CLKSRC options */
82 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
83 /* from MCLK1 to MCLK2 */
84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
85 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
86 /* available at the MCLK2 pin */
87 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
88 /* at the MCLK2 pin */
89
90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
91
92 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
93 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
95 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
96 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
97 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
98 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
99 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
100 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
102
103 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
104 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
105 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
106 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
107 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
108 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
109 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
110 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
111
112 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
113 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
114 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
115 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
116 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
117 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
118 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
119 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
120 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
121 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
122 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
123 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
124 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
125 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
126 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
127
128 /* ID Register Bit Designations (AD7192_REG_ID) */
129 #define CHIPID_AD7190 0x4
130 #define CHIPID_AD7192 0x0
131 #define CHIPID_AD7193 0x2
132 #define CHIPID_AD7195 0x6
133 #define AD7192_ID_MASK 0x0F
134
135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
137 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
138 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
139 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
140 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
141 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
142 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
143
144 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
145 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
146 #define AD7192_INT_FREQ_MHZ 4915200
147
148 #define AD7192_NO_SYNC_FILTER 1
149 #define AD7192_SYNC3_FILTER 3
150 #define AD7192_SYNC4_FILTER 4
151
152 /* NOTE:
153 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
154 * In order to avoid contentions on the SPI bus, it's therefore necessary
155 * to use spi bus locking.
156 *
157 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
158 */
159
160 enum {
161 AD7192_SYSCALIB_ZERO_SCALE,
162 AD7192_SYSCALIB_FULL_SCALE,
163 };
164
165 enum {
166 ID_AD7190,
167 ID_AD7192,
168 ID_AD7193,
169 ID_AD7195,
170 };
171
172 struct ad7192_chip_info {
173 unsigned int chip_id;
174 const char *name;
175 };
176
177 struct ad7192_state {
178 const struct ad7192_chip_info *chip_info;
179 struct regulator *avdd;
180 struct regulator *vref;
181 struct clk *mclk;
182 u16 int_vref_mv;
183 u32 fclk;
184 u32 f_order;
185 u32 mode;
186 u32 conf;
187 u32 scale_avail[8][2];
188 u8 gpocon;
189 u8 clock_sel;
190 struct mutex lock; /* protect sensor state */
191 u8 syscalib_mode[8];
192
193 struct ad_sigma_delta sd;
194 };
195
196 static const char * const ad7192_syscalib_modes[] = {
197 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
198 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
199 };
200
ad7192_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)201 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
202 const struct iio_chan_spec *chan,
203 unsigned int mode)
204 {
205 struct ad7192_state *st = iio_priv(indio_dev);
206
207 st->syscalib_mode[chan->channel] = mode;
208
209 return 0;
210 }
211
ad7192_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)212 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
213 const struct iio_chan_spec *chan)
214 {
215 struct ad7192_state *st = iio_priv(indio_dev);
216
217 return st->syscalib_mode[chan->channel];
218 }
219
ad7192_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)220 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
221 uintptr_t private,
222 const struct iio_chan_spec *chan,
223 const char *buf, size_t len)
224 {
225 struct ad7192_state *st = iio_priv(indio_dev);
226 bool sys_calib;
227 int ret, temp;
228
229 ret = kstrtobool(buf, &sys_calib);
230 if (ret)
231 return ret;
232
233 temp = st->syscalib_mode[chan->channel];
234 if (sys_calib) {
235 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
236 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
237 chan->address);
238 else
239 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
240 chan->address);
241 }
242
243 return ret ? ret : len;
244 }
245
246 static const struct iio_enum ad7192_syscalib_mode_enum = {
247 .items = ad7192_syscalib_modes,
248 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
249 .set = ad7192_set_syscalib_mode,
250 .get = ad7192_get_syscalib_mode
251 };
252
253 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
254 {
255 .name = "sys_calibration",
256 .write = ad7192_write_syscalib,
257 .shared = IIO_SEPARATE,
258 },
259 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
260 &ad7192_syscalib_mode_enum),
261 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
262 &ad7192_syscalib_mode_enum),
263 {}
264 };
265
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)266 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
267 {
268 return container_of(sd, struct ad7192_state, sd);
269 }
270
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)271 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
272 {
273 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
274
275 st->conf &= ~AD7192_CONF_CHAN_MASK;
276 st->conf |= AD7192_CONF_CHAN(channel);
277
278 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
279 }
280
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)281 static int ad7192_set_mode(struct ad_sigma_delta *sd,
282 enum ad_sigma_delta_mode mode)
283 {
284 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
285
286 st->mode &= ~AD7192_MODE_SEL_MASK;
287 st->mode |= AD7192_MODE_SEL(mode);
288
289 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
290 }
291
ad7192_append_status(struct ad_sigma_delta * sd,bool append)292 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
293 {
294 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
295 unsigned int mode = st->mode;
296 int ret;
297
298 mode &= ~AD7192_MODE_STA_MASK;
299 mode |= AD7192_MODE_STA(append);
300
301 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
302 if (ret < 0)
303 return ret;
304
305 st->mode = mode;
306
307 return 0;
308 }
309
ad7192_disable_all(struct ad_sigma_delta * sd)310 static int ad7192_disable_all(struct ad_sigma_delta *sd)
311 {
312 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
313 u32 conf = st->conf;
314 int ret;
315
316 conf &= ~AD7192_CONF_CHAN_MASK;
317
318 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
319 if (ret < 0)
320 return ret;
321
322 st->conf = conf;
323
324 return 0;
325 }
326
327 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
328 .set_channel = ad7192_set_channel,
329 .append_status = ad7192_append_status,
330 .disable_all = ad7192_disable_all,
331 .set_mode = ad7192_set_mode,
332 .has_registers = true,
333 .addr_shift = 3,
334 .read_mask = BIT(6),
335 .status_ch_mask = GENMASK(3, 0),
336 .num_slots = 4,
337 .irq_flags = IRQF_TRIGGER_FALLING,
338 };
339
340 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
341 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
342 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
343 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
344 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
345 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
346 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
347 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
348 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
349 };
350
ad7192_calibrate_all(struct ad7192_state * st)351 static int ad7192_calibrate_all(struct ad7192_state *st)
352 {
353 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
354 ARRAY_SIZE(ad7192_calib_arr));
355 }
356
ad7192_valid_external_frequency(u32 freq)357 static inline bool ad7192_valid_external_frequency(u32 freq)
358 {
359 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
360 freq <= AD7192_EXT_FREQ_MHZ_MAX);
361 }
362
ad7192_of_clock_select(struct ad7192_state * st)363 static int ad7192_of_clock_select(struct ad7192_state *st)
364 {
365 struct device_node *np = st->sd.spi->dev.of_node;
366 unsigned int clock_sel;
367
368 clock_sel = AD7192_CLK_INT;
369
370 /* use internal clock */
371 if (!st->mclk) {
372 if (of_property_read_bool(np, "adi,int-clock-output-enable"))
373 clock_sel = AD7192_CLK_INT_CO;
374 } else {
375 if (of_property_read_bool(np, "adi,clock-xtal"))
376 clock_sel = AD7192_CLK_EXT_MCLK1_2;
377 else
378 clock_sel = AD7192_CLK_EXT_MCLK2;
379 }
380
381 return clock_sel;
382 }
383
ad7192_setup(struct iio_dev * indio_dev,struct device_node * np)384 static int ad7192_setup(struct iio_dev *indio_dev, struct device_node *np)
385 {
386 struct ad7192_state *st = iio_priv(indio_dev);
387 bool rej60_en, refin2_en;
388 bool buf_en, bipolar, burnout_curr_en;
389 unsigned long long scale_uv;
390 int i, ret, id;
391
392 /* reset the serial interface */
393 ret = ad_sd_reset(&st->sd, 48);
394 if (ret < 0)
395 return ret;
396 usleep_range(500, 1000); /* Wait for at least 500us */
397
398 /* write/read test for device presence */
399 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
400 if (ret)
401 return ret;
402
403 id &= AD7192_ID_MASK;
404
405 if (id != st->chip_info->chip_id)
406 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X != 0x%X)\n",
407 id, st->chip_info->chip_id);
408
409 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
410 AD7192_MODE_CLKSRC(st->clock_sel) |
411 AD7192_MODE_RATE(480);
412
413 st->conf = AD7192_CONF_GAIN(0);
414
415 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
416 if (rej60_en)
417 st->mode |= AD7192_MODE_REJ60;
418
419 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
420 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
421 st->conf |= AD7192_CONF_REFSEL;
422
423 st->conf &= ~AD7192_CONF_CHOP;
424 st->f_order = AD7192_NO_SYNC_FILTER;
425
426 buf_en = of_property_read_bool(np, "adi,buffer-enable");
427 if (buf_en)
428 st->conf |= AD7192_CONF_BUF;
429
430 bipolar = of_property_read_bool(np, "bipolar");
431 if (!bipolar)
432 st->conf |= AD7192_CONF_UNIPOLAR;
433
434 burnout_curr_en = of_property_read_bool(np,
435 "adi,burnout-currents-enable");
436 if (burnout_curr_en && buf_en) {
437 st->conf |= AD7192_CONF_BURN;
438 } else if (burnout_curr_en) {
439 dev_warn(&st->sd.spi->dev,
440 "Can't enable burnout currents: see CHOP or buffer\n");
441 }
442
443 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
444 if (ret)
445 return ret;
446
447 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
448 if (ret)
449 return ret;
450
451 ret = ad7192_calibrate_all(st);
452 if (ret)
453 return ret;
454
455 /* Populate available ADC input ranges */
456 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
457 scale_uv = ((u64)st->int_vref_mv * 100000000)
458 >> (indio_dev->channels[0].scan_type.realbits -
459 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
460 scale_uv >>= i;
461
462 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
463 st->scale_avail[i][0] = scale_uv;
464 }
465
466 return 0;
467 }
468
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)469 static ssize_t ad7192_show_ac_excitation(struct device *dev,
470 struct device_attribute *attr,
471 char *buf)
472 {
473 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
474 struct ad7192_state *st = iio_priv(indio_dev);
475
476 return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX));
477 }
478
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)479 static ssize_t ad7192_show_bridge_switch(struct device *dev,
480 struct device_attribute *attr,
481 char *buf)
482 {
483 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
484 struct ad7192_state *st = iio_priv(indio_dev);
485
486 return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
487 }
488
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)489 static ssize_t ad7192_set(struct device *dev,
490 struct device_attribute *attr,
491 const char *buf,
492 size_t len)
493 {
494 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
495 struct ad7192_state *st = iio_priv(indio_dev);
496 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
497 int ret;
498 bool val;
499
500 ret = kstrtobool(buf, &val);
501 if (ret < 0)
502 return ret;
503
504 ret = iio_device_claim_direct_mode(indio_dev);
505 if (ret)
506 return ret;
507
508 switch ((u32)this_attr->address) {
509 case AD7192_REG_GPOCON:
510 if (val)
511 st->gpocon |= AD7192_GPOCON_BPDSW;
512 else
513 st->gpocon &= ~AD7192_GPOCON_BPDSW;
514
515 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
516 break;
517 case AD7192_REG_CONF:
518 if (val)
519 st->conf |= AD7192_CONF_ACX;
520 else
521 st->conf &= ~AD7192_CONF_ACX;
522
523 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
524 break;
525 default:
526 ret = -EINVAL;
527 }
528
529 iio_device_release_direct_mode(indio_dev);
530
531 return ret ? ret : len;
532 }
533
ad7192_get_available_filter_freq(struct ad7192_state * st,int * freq)534 static void ad7192_get_available_filter_freq(struct ad7192_state *st,
535 int *freq)
536 {
537 unsigned int fadc;
538
539 /* Formulas for filter at page 25 of the datasheet */
540 fadc = DIV_ROUND_CLOSEST(st->fclk,
541 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
542 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
543
544 fadc = DIV_ROUND_CLOSEST(st->fclk,
545 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
546 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
547
548 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
549 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
550 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
551 }
552
ad7192_show_filter_avail(struct device * dev,struct device_attribute * attr,char * buf)553 static ssize_t ad7192_show_filter_avail(struct device *dev,
554 struct device_attribute *attr,
555 char *buf)
556 {
557 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
558 struct ad7192_state *st = iio_priv(indio_dev);
559 unsigned int freq_avail[4], i;
560 size_t len = 0;
561
562 ad7192_get_available_filter_freq(st, freq_avail);
563
564 for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
565 len += sysfs_emit_at(buf, len, "%d.%03d ", freq_avail[i] / 1000,
566 freq_avail[i] % 1000);
567
568 buf[len - 1] = '\n';
569
570 return len;
571 }
572
573 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
574 0444, ad7192_show_filter_avail, NULL, 0);
575
576 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
577 ad7192_show_bridge_switch, ad7192_set,
578 AD7192_REG_GPOCON);
579
580 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
581 ad7192_show_ac_excitation, ad7192_set,
582 AD7192_REG_CONF);
583
584 static struct attribute *ad7192_attributes[] = {
585 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
586 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
587 NULL
588 };
589
590 static const struct attribute_group ad7192_attribute_group = {
591 .attrs = ad7192_attributes,
592 };
593
594 static struct attribute *ad7195_attributes[] = {
595 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
596 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
597 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
598 NULL
599 };
600
601 static const struct attribute_group ad7195_attribute_group = {
602 .attrs = ad7195_attributes,
603 };
604
ad7192_get_temp_scale(bool unipolar)605 static unsigned int ad7192_get_temp_scale(bool unipolar)
606 {
607 return unipolar ? 2815 * 2 : 2815;
608 }
609
ad7192_set_3db_filter_freq(struct ad7192_state * st,int val,int val2)610 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
611 int val, int val2)
612 {
613 int freq_avail[4], i, ret, freq;
614 unsigned int diff_new, diff_old;
615 int idx = 0;
616
617 diff_old = U32_MAX;
618 freq = val * 1000 + val2;
619
620 ad7192_get_available_filter_freq(st, freq_avail);
621
622 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
623 diff_new = abs(freq - freq_avail[i]);
624 if (diff_new < diff_old) {
625 diff_old = diff_new;
626 idx = i;
627 }
628 }
629
630 switch (idx) {
631 case 0:
632 st->f_order = AD7192_SYNC4_FILTER;
633 st->mode &= ~AD7192_MODE_SINC3;
634
635 st->conf |= AD7192_CONF_CHOP;
636 break;
637 case 1:
638 st->f_order = AD7192_SYNC3_FILTER;
639 st->mode |= AD7192_MODE_SINC3;
640
641 st->conf |= AD7192_CONF_CHOP;
642 break;
643 case 2:
644 st->f_order = AD7192_NO_SYNC_FILTER;
645 st->mode &= ~AD7192_MODE_SINC3;
646
647 st->conf &= ~AD7192_CONF_CHOP;
648 break;
649 case 3:
650 st->f_order = AD7192_NO_SYNC_FILTER;
651 st->mode |= AD7192_MODE_SINC3;
652
653 st->conf &= ~AD7192_CONF_CHOP;
654 break;
655 }
656
657 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
658 if (ret < 0)
659 return ret;
660
661 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
662 }
663
ad7192_get_3db_filter_freq(struct ad7192_state * st)664 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
665 {
666 unsigned int fadc;
667
668 fadc = DIV_ROUND_CLOSEST(st->fclk,
669 st->f_order * AD7192_MODE_RATE(st->mode));
670
671 if (st->conf & AD7192_CONF_CHOP)
672 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
673 if (st->mode & AD7192_MODE_SINC3)
674 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
675 else
676 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
677 }
678
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)679 static int ad7192_read_raw(struct iio_dev *indio_dev,
680 struct iio_chan_spec const *chan,
681 int *val,
682 int *val2,
683 long m)
684 {
685 struct ad7192_state *st = iio_priv(indio_dev);
686 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
687
688 switch (m) {
689 case IIO_CHAN_INFO_RAW:
690 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
691 case IIO_CHAN_INFO_SCALE:
692 switch (chan->type) {
693 case IIO_VOLTAGE:
694 mutex_lock(&st->lock);
695 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
696 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
697 mutex_unlock(&st->lock);
698 return IIO_VAL_INT_PLUS_NANO;
699 case IIO_TEMP:
700 *val = 0;
701 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
702 return IIO_VAL_INT_PLUS_NANO;
703 default:
704 return -EINVAL;
705 }
706 case IIO_CHAN_INFO_OFFSET:
707 if (!unipolar)
708 *val = -(1 << (chan->scan_type.realbits - 1));
709 else
710 *val = 0;
711 /* Kelvin to Celsius */
712 if (chan->type == IIO_TEMP)
713 *val -= 273 * ad7192_get_temp_scale(unipolar);
714 return IIO_VAL_INT;
715 case IIO_CHAN_INFO_SAMP_FREQ:
716 *val = st->fclk /
717 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
718 return IIO_VAL_INT;
719 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
720 *val = ad7192_get_3db_filter_freq(st);
721 *val2 = 1000;
722 return IIO_VAL_FRACTIONAL;
723 }
724
725 return -EINVAL;
726 }
727
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)728 static int ad7192_write_raw(struct iio_dev *indio_dev,
729 struct iio_chan_spec const *chan,
730 int val,
731 int val2,
732 long mask)
733 {
734 struct ad7192_state *st = iio_priv(indio_dev);
735 int ret, i, div;
736 unsigned int tmp;
737
738 ret = iio_device_claim_direct_mode(indio_dev);
739 if (ret)
740 return ret;
741
742 switch (mask) {
743 case IIO_CHAN_INFO_SCALE:
744 ret = -EINVAL;
745 mutex_lock(&st->lock);
746 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
747 if (val2 == st->scale_avail[i][1]) {
748 ret = 0;
749 tmp = st->conf;
750 st->conf &= ~AD7192_CONF_GAIN(-1);
751 st->conf |= AD7192_CONF_GAIN(i);
752 if (tmp == st->conf)
753 break;
754 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
755 3, st->conf);
756 ad7192_calibrate_all(st);
757 break;
758 }
759 mutex_unlock(&st->lock);
760 break;
761 case IIO_CHAN_INFO_SAMP_FREQ:
762 if (!val) {
763 ret = -EINVAL;
764 break;
765 }
766
767 div = st->fclk / (val * st->f_order * 1024);
768 if (div < 1 || div > 1023) {
769 ret = -EINVAL;
770 break;
771 }
772
773 st->mode &= ~AD7192_MODE_RATE(-1);
774 st->mode |= AD7192_MODE_RATE(div);
775 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
776 break;
777 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
778 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
779 break;
780 default:
781 ret = -EINVAL;
782 }
783
784 iio_device_release_direct_mode(indio_dev);
785
786 return ret;
787 }
788
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)789 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
790 struct iio_chan_spec const *chan,
791 long mask)
792 {
793 switch (mask) {
794 case IIO_CHAN_INFO_SCALE:
795 return IIO_VAL_INT_PLUS_NANO;
796 case IIO_CHAN_INFO_SAMP_FREQ:
797 return IIO_VAL_INT;
798 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
799 return IIO_VAL_INT_PLUS_MICRO;
800 default:
801 return -EINVAL;
802 }
803 }
804
ad7192_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)805 static int ad7192_read_avail(struct iio_dev *indio_dev,
806 struct iio_chan_spec const *chan,
807 const int **vals, int *type, int *length,
808 long mask)
809 {
810 struct ad7192_state *st = iio_priv(indio_dev);
811
812 switch (mask) {
813 case IIO_CHAN_INFO_SCALE:
814 *vals = (int *)st->scale_avail;
815 *type = IIO_VAL_INT_PLUS_NANO;
816 /* Values are stored in a 2D matrix */
817 *length = ARRAY_SIZE(st->scale_avail) * 2;
818
819 return IIO_AVAIL_LIST;
820 }
821
822 return -EINVAL;
823 }
824
ad7192_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)825 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
826 {
827 struct ad7192_state *st = iio_priv(indio_dev);
828 u32 conf = st->conf;
829 int ret;
830 int i;
831
832 conf &= ~AD7192_CONF_CHAN_MASK;
833 for_each_set_bit(i, scan_mask, 8)
834 conf |= AD7192_CONF_CHAN(i);
835
836 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
837 if (ret < 0)
838 return ret;
839
840 st->conf = conf;
841
842 return 0;
843 }
844
845 static const struct iio_info ad7192_info = {
846 .read_raw = ad7192_read_raw,
847 .write_raw = ad7192_write_raw,
848 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
849 .read_avail = ad7192_read_avail,
850 .attrs = &ad7192_attribute_group,
851 .validate_trigger = ad_sd_validate_trigger,
852 .update_scan_mode = ad7192_update_scan_mode,
853 };
854
855 static const struct iio_info ad7195_info = {
856 .read_raw = ad7192_read_raw,
857 .write_raw = ad7192_write_raw,
858 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
859 .read_avail = ad7192_read_avail,
860 .attrs = &ad7195_attribute_group,
861 .validate_trigger = ad_sd_validate_trigger,
862 .update_scan_mode = ad7192_update_scan_mode,
863 };
864
865 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
866 _type, _mask_type_av, _ext_info) \
867 { \
868 .type = (_type), \
869 .differential = ((_channel2) == -1 ? 0 : 1), \
870 .indexed = 1, \
871 .channel = (_channel1), \
872 .channel2 = (_channel2), \
873 .address = (_address), \
874 .extend_name = (_extend_name), \
875 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
876 BIT(IIO_CHAN_INFO_OFFSET), \
877 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
878 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
879 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
880 .info_mask_shared_by_type_available = (_mask_type_av), \
881 .ext_info = (_ext_info), \
882 .scan_index = (_si), \
883 .scan_type = { \
884 .sign = 'u', \
885 .realbits = 24, \
886 .storagebits = 32, \
887 .endianness = IIO_BE, \
888 }, \
889 }
890
891 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
892 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
893 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
894 ad7192_calibsys_ext_info)
895
896 #define AD719x_CHANNEL(_si, _channel1, _address) \
897 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
898 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
899
900 #define AD719x_TEMP_CHANNEL(_si, _address) \
901 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
902
903 static const struct iio_chan_spec ad7192_channels[] = {
904 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
905 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
906 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
907 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
908 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
909 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
910 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
911 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
912 IIO_CHAN_SOFT_TIMESTAMP(8),
913 };
914
915 static const struct iio_chan_spec ad7193_channels[] = {
916 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
917 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
918 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
919 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
920 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
921 AD719x_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
922 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
923 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
924 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
925 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
926 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
927 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
928 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
929 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
930 IIO_CHAN_SOFT_TIMESTAMP(14),
931 };
932
933 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
934 [ID_AD7190] = {
935 .chip_id = CHIPID_AD7190,
936 .name = "ad7190",
937 },
938 [ID_AD7192] = {
939 .chip_id = CHIPID_AD7192,
940 .name = "ad7192",
941 },
942 [ID_AD7193] = {
943 .chip_id = CHIPID_AD7193,
944 .name = "ad7193",
945 },
946 [ID_AD7195] = {
947 .chip_id = CHIPID_AD7195,
948 .name = "ad7195",
949 },
950 };
951
ad7192_channels_config(struct iio_dev * indio_dev)952 static int ad7192_channels_config(struct iio_dev *indio_dev)
953 {
954 struct ad7192_state *st = iio_priv(indio_dev);
955
956 switch (st->chip_info->chip_id) {
957 case CHIPID_AD7193:
958 indio_dev->channels = ad7193_channels;
959 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
960 break;
961 default:
962 indio_dev->channels = ad7192_channels;
963 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
964 break;
965 }
966
967 return 0;
968 }
969
ad7192_reg_disable(void * reg)970 static void ad7192_reg_disable(void *reg)
971 {
972 regulator_disable(reg);
973 }
974
ad7192_probe(struct spi_device * spi)975 static int ad7192_probe(struct spi_device *spi)
976 {
977 struct ad7192_state *st;
978 struct iio_dev *indio_dev;
979 int ret;
980
981 if (!spi->irq) {
982 dev_err(&spi->dev, "no IRQ?\n");
983 return -ENODEV;
984 }
985
986 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
987 if (!indio_dev)
988 return -ENOMEM;
989
990 st = iio_priv(indio_dev);
991
992 mutex_init(&st->lock);
993
994 st->avdd = devm_regulator_get(&spi->dev, "avdd");
995 if (IS_ERR(st->avdd))
996 return PTR_ERR(st->avdd);
997
998 ret = regulator_enable(st->avdd);
999 if (ret) {
1000 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
1001 return ret;
1002 }
1003
1004 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd);
1005 if (ret)
1006 return ret;
1007
1008 ret = devm_regulator_get_enable(&spi->dev, "dvdd");
1009 if (ret)
1010 return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n");
1011
1012 st->vref = devm_regulator_get_optional(&spi->dev, "vref");
1013 if (IS_ERR(st->vref)) {
1014 if (PTR_ERR(st->vref) != -ENODEV)
1015 return PTR_ERR(st->vref);
1016
1017 ret = regulator_get_voltage(st->avdd);
1018 if (ret < 0)
1019 return dev_err_probe(&spi->dev, ret,
1020 "Device tree error, AVdd voltage undefined\n");
1021 } else {
1022 ret = regulator_enable(st->vref);
1023 if (ret) {
1024 dev_err(&spi->dev, "Failed to enable specified Vref supply\n");
1025 return ret;
1026 }
1027
1028 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->vref);
1029 if (ret)
1030 return ret;
1031
1032 ret = regulator_get_voltage(st->vref);
1033 if (ret < 0)
1034 return dev_err_probe(&spi->dev, ret,
1035 "Device tree error, Vref voltage undefined\n");
1036 }
1037 st->int_vref_mv = ret / 1000;
1038
1039 st->chip_info = of_device_get_match_data(&spi->dev);
1040 if (!st->chip_info)
1041 st->chip_info = (void *)spi_get_device_id(spi)->driver_data;
1042 indio_dev->name = st->chip_info->name;
1043 indio_dev->modes = INDIO_DIRECT_MODE;
1044
1045 ret = ad7192_channels_config(indio_dev);
1046 if (ret < 0)
1047 return ret;
1048
1049 if (st->chip_info->chip_id == CHIPID_AD7195)
1050 indio_dev->info = &ad7195_info;
1051 else
1052 indio_dev->info = &ad7192_info;
1053
1054 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
1055 if (ret)
1056 return ret;
1057
1058 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1059 if (ret)
1060 return ret;
1061
1062 st->fclk = AD7192_INT_FREQ_MHZ;
1063
1064 st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk");
1065 if (IS_ERR(st->mclk))
1066 return PTR_ERR(st->mclk);
1067
1068 st->clock_sel = ad7192_of_clock_select(st);
1069
1070 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
1071 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
1072 st->fclk = clk_get_rate(st->mclk);
1073 if (!ad7192_valid_external_frequency(st->fclk)) {
1074 dev_err(&spi->dev,
1075 "External clock frequency out of bounds\n");
1076 return -EINVAL;
1077 }
1078 }
1079
1080 ret = ad7192_setup(indio_dev, spi->dev.of_node);
1081 if (ret)
1082 return ret;
1083
1084 return devm_iio_device_register(&spi->dev, indio_dev);
1085 }
1086
1087 static const struct of_device_id ad7192_of_match[] = {
1088 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1089 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1090 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1091 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1092 {}
1093 };
1094 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1095
1096 static const struct spi_device_id ad7192_ids[] = {
1097 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1098 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1099 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1100 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1101 {}
1102 };
1103 MODULE_DEVICE_TABLE(spi, ad7192_ids);
1104
1105 static struct spi_driver ad7192_driver = {
1106 .driver = {
1107 .name = "ad7192",
1108 .of_match_table = ad7192_of_match,
1109 },
1110 .probe = ad7192_probe,
1111 .id_table = ad7192_ids,
1112 };
1113 module_spi_driver(ad7192_driver);
1114
1115 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1116 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
1117 MODULE_LICENSE("GPL v2");
1118 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
1119
