Searched refs:wrm_reg (Results 1 – 3 of 3) sorted by relevance
881 op_input.wrm_reg.reg0 = reg0; in amdgpu_mes_reg_write_reg_wait()882 op_input.wrm_reg.reg1 = reg1; in amdgpu_mes_reg_write_reg_wait()883 op_input.wrm_reg.ref = ref; in amdgpu_mes_reg_write_reg_wait()884 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_write_reg_wait()907 op_input.wrm_reg.reg0 = reg; in amdgpu_mes_reg_wait()908 op_input.wrm_reg.ref = val; in amdgpu_mes_reg_wait()909 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_wait()
319 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()320 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()321 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()327 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()328 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()329 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()330 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
282 } wrm_reg; member
