1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * 8250-core based driver for the OMAP internal UART
4 *
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 *
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/serial_8250.h>
16 #include <linux/serial_reg.h>
17 #include <linux/tty_flip.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_irq.h>
24 #include <linux/delay.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/console.h>
27 #include <linux/pm_qos.h>
28 #include <linux/pm_wakeirq.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sys_soc.h>
31
32 #include "8250.h"
33
34 #define DEFAULT_CLK_SPEED 48000000
35
36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
38 #define OMAP_DMA_TX_KICK (1 << 2)
39 /*
40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
41 * The same errata is applicable to AM335x and DRA7x processors too.
42 */
43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
44 #define UART_HAS_EFR2 BIT(4)
45 #define UART_HAS_RHR_IT_DIS BIT(5)
46 #define UART_RX_TIMEOUT_QUIRK BIT(6)
47
48 #define OMAP_UART_FCR_RX_TRIG 6
49 #define OMAP_UART_FCR_TX_TRIG 4
50
51 /* SCR register bitmasks */
52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
54 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
55 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
56 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
57 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
58
59 /* MVR register bitmasks */
60 #define OMAP_UART_MVR_SCHEME_SHIFT 30
61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
63 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
64 #define OMAP_UART_MVR_MAJ_MASK 0x700
65 #define OMAP_UART_MVR_MAJ_SHIFT 8
66 #define OMAP_UART_MVR_MIN_MASK 0x3f
67
68 /* SYSC register bitmasks */
69 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
70
71 /* SYSS register bitmasks */
72 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
73
74 #define UART_TI752_TLR_TX 0
75 #define UART_TI752_TLR_RX 4
76
77 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
78 #define TRIGGER_FCR_MASK(x) (x & 3)
79
80 /* Enable XON/XOFF flow control on output */
81 #define OMAP_UART_SW_TX 0x08
82 /* Enable XON/XOFF flow control on input */
83 #define OMAP_UART_SW_RX 0x02
84
85 #define OMAP_UART_WER_MOD_WKUP 0x7f
86 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
87
88 #define TX_TRIGGER 1
89 #define RX_TRIGGER 48
90
91 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
92 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
93
94 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
95
96 #define OMAP_UART_REV_46 0x0406
97 #define OMAP_UART_REV_52 0x0502
98 #define OMAP_UART_REV_63 0x0603
99
100 /* Interrupt Enable Register 2 */
101 #define UART_OMAP_IER2 0x1B
102 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
103
104 /* Enhanced features register 2 */
105 #define UART_OMAP_EFR2 0x23
106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
107
108 /* RX FIFO occupancy indicator */
109 #define UART_OMAP_RX_LVL 0x19
110
111 struct omap8250_priv {
112 int line;
113 u8 habit;
114 u8 mdr1;
115 u8 efr;
116 u8 scr;
117 u8 wer;
118 u8 xon;
119 u8 xoff;
120 u8 delayed_restore;
121 u16 quot;
122
123 u8 tx_trigger;
124 u8 rx_trigger;
125 bool is_suspending;
126 int wakeirq;
127 int wakeups_enabled;
128 u32 latency;
129 u32 calc_latency;
130 struct pm_qos_request pm_qos_request;
131 struct work_struct qos_work;
132 struct uart_8250_dma omap8250_dma;
133 spinlock_t rx_dma_lock;
134 bool rx_dma_broken;
135 bool throttled;
136 };
137
138 struct omap8250_dma_params {
139 u32 rx_size;
140 u8 rx_trigger;
141 u8 tx_trigger;
142 };
143
144 struct omap8250_platdata {
145 struct omap8250_dma_params *dma_params;
146 u8 habit;
147 };
148
149 #ifdef CONFIG_SERIAL_8250_DMA
150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
151 #else
omap_8250_rx_dma_flush(struct uart_8250_port * p)152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
153 #endif
154
uart_read(struct uart_8250_port * up,u32 reg)155 static u32 uart_read(struct uart_8250_port *up, u32 reg)
156 {
157 return readl(up->port.membase + (reg << up->port.regshift));
158 }
159
160 /*
161 * Called on runtime PM resume path from omap8250_restore_regs(), and
162 * omap8250_set_mctrl().
163 */
__omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)164 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
165 {
166 struct uart_8250_port *up = up_to_u8250p(port);
167 struct omap8250_priv *priv = up->port.private_data;
168 u8 lcr;
169
170 serial8250_do_set_mctrl(port, mctrl);
171
172 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
173 /*
174 * Turn off autoRTS if RTS is lowered and restore autoRTS
175 * setting if RTS is raised
176 */
177 lcr = serial_in(up, UART_LCR);
178 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
179 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
180 priv->efr |= UART_EFR_RTS;
181 else
182 priv->efr &= ~UART_EFR_RTS;
183 serial_out(up, UART_EFR, priv->efr);
184 serial_out(up, UART_LCR, lcr);
185 }
186 }
187
omap8250_set_mctrl(struct uart_port * port,unsigned int mctrl)188 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
189 {
190 int err;
191
192 err = pm_runtime_resume_and_get(port->dev);
193 if (err)
194 return;
195
196 __omap8250_set_mctrl(port, mctrl);
197
198 pm_runtime_mark_last_busy(port->dev);
199 pm_runtime_put_autosuspend(port->dev);
200 }
201
202 /*
203 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
204 * The access to uart register after MDR1 Access
205 * causes UART to corrupt data.
206 *
207 * Need a delay =
208 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
209 * give 10 times as much
210 */
omap_8250_mdr1_errataset(struct uart_8250_port * up,struct omap8250_priv * priv)211 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
212 struct omap8250_priv *priv)
213 {
214 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
215 udelay(2);
216 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
217 UART_FCR_CLEAR_RCVR);
218 }
219
omap_8250_get_divisor(struct uart_port * port,unsigned int baud,struct omap8250_priv * priv)220 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
221 struct omap8250_priv *priv)
222 {
223 unsigned int uartclk = port->uartclk;
224 unsigned int div_13, div_16;
225 unsigned int abs_d13, abs_d16;
226
227 /*
228 * Old custom speed handling.
229 */
230 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
231 priv->quot = port->custom_divisor & UART_DIV_MAX;
232 /*
233 * I assume that nobody is using this. But hey, if somebody
234 * would like to specify the divisor _and_ the mode then the
235 * driver is ready and waiting for it.
236 */
237 if (port->custom_divisor & (1 << 16))
238 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
239 else
240 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
241 return;
242 }
243 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
244 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
245
246 if (!div_13)
247 div_13 = 1;
248 if (!div_16)
249 div_16 = 1;
250
251 abs_d13 = abs(baud - uartclk / 13 / div_13);
252 abs_d16 = abs(baud - uartclk / 16 / div_16);
253
254 if (abs_d13 >= abs_d16) {
255 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
256 priv->quot = div_16;
257 } else {
258 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
259 priv->quot = div_13;
260 }
261 }
262
omap8250_update_scr(struct uart_8250_port * up,struct omap8250_priv * priv)263 static void omap8250_update_scr(struct uart_8250_port *up,
264 struct omap8250_priv *priv)
265 {
266 u8 old_scr;
267
268 old_scr = serial_in(up, UART_OMAP_SCR);
269 if (old_scr == priv->scr)
270 return;
271
272 /*
273 * The manual recommends not to enable the DMA mode selector in the SCR
274 * (instead of the FCR) register _and_ selecting the DMA mode as one
275 * register write because this may lead to malfunction.
276 */
277 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
278 serial_out(up, UART_OMAP_SCR,
279 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
280 serial_out(up, UART_OMAP_SCR, priv->scr);
281 }
282
omap8250_update_mdr1(struct uart_8250_port * up,struct omap8250_priv * priv)283 static void omap8250_update_mdr1(struct uart_8250_port *up,
284 struct omap8250_priv *priv)
285 {
286 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
287 omap_8250_mdr1_errataset(up, priv);
288 else
289 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
290 }
291
omap8250_restore_regs(struct uart_8250_port * up)292 static void omap8250_restore_regs(struct uart_8250_port *up)
293 {
294 struct omap8250_priv *priv = up->port.private_data;
295 struct uart_8250_dma *dma = up->dma;
296 u8 mcr = serial8250_in_MCR(up);
297
298 if (dma && dma->tx_running) {
299 /*
300 * TCSANOW requests the change to occur immediately however if
301 * we have a TX-DMA operation in progress then it has been
302 * observed that it might stall and never complete. Therefore we
303 * delay DMA completes to prevent this hang from happen.
304 */
305 priv->delayed_restore = 1;
306 return;
307 }
308
309 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
310 serial_out(up, UART_EFR, UART_EFR_ECB);
311
312 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
313 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
314 serial_out(up, UART_FCR, up->fcr);
315
316 omap8250_update_scr(up, priv);
317
318 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
319
320 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
321 OMAP_UART_TCR_HALT(52));
322 serial_out(up, UART_TI752_TLR,
323 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
324 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
325
326 serial_out(up, UART_LCR, 0);
327
328 /* drop TCR + TLR access, we setup XON/XOFF later */
329 serial8250_out_MCR(up, mcr);
330
331 serial_out(up, UART_IER, up->ier);
332
333 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
334 serial_dl_write(up, priv->quot);
335
336 serial_out(up, UART_EFR, priv->efr);
337
338 /* Configure flow control */
339 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
340 serial_out(up, UART_XON1, priv->xon);
341 serial_out(up, UART_XOFF1, priv->xoff);
342
343 serial_out(up, UART_LCR, up->lcr);
344
345 omap8250_update_mdr1(up, priv);
346
347 __omap8250_set_mctrl(&up->port, up->port.mctrl);
348
349 if (up->port.rs485.flags & SER_RS485_ENABLED)
350 serial8250_em485_stop_tx(up);
351 }
352
353 /*
354 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
355 * some differences in how we want to handle flow control.
356 */
omap_8250_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)357 static void omap_8250_set_termios(struct uart_port *port,
358 struct ktermios *termios,
359 const struct ktermios *old)
360 {
361 struct uart_8250_port *up = up_to_u8250p(port);
362 struct omap8250_priv *priv = up->port.private_data;
363 unsigned char cval = 0;
364 unsigned int baud;
365
366 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
367
368 if (termios->c_cflag & CSTOPB)
369 cval |= UART_LCR_STOP;
370 if (termios->c_cflag & PARENB)
371 cval |= UART_LCR_PARITY;
372 if (!(termios->c_cflag & PARODD))
373 cval |= UART_LCR_EPAR;
374 if (termios->c_cflag & CMSPAR)
375 cval |= UART_LCR_SPAR;
376
377 /*
378 * Ask the core to calculate the divisor for us.
379 */
380 baud = uart_get_baud_rate(port, termios, old,
381 port->uartclk / 16 / UART_DIV_MAX,
382 port->uartclk / 13);
383 omap_8250_get_divisor(port, baud, priv);
384
385 /*
386 * Ok, we're now changing the port state. Do it with
387 * interrupts disabled.
388 */
389 pm_runtime_get_sync(port->dev);
390 spin_lock_irq(&port->lock);
391
392 /*
393 * Update the per-port timeout.
394 */
395 uart_update_timeout(port, termios->c_cflag, baud);
396
397 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
398 if (termios->c_iflag & INPCK)
399 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
400 if (termios->c_iflag & (IGNBRK | PARMRK))
401 up->port.read_status_mask |= UART_LSR_BI;
402
403 /*
404 * Characters to ignore
405 */
406 up->port.ignore_status_mask = 0;
407 if (termios->c_iflag & IGNPAR)
408 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
409 if (termios->c_iflag & IGNBRK) {
410 up->port.ignore_status_mask |= UART_LSR_BI;
411 /*
412 * If we're ignoring parity and break indicators,
413 * ignore overruns too (for real raw support).
414 */
415 if (termios->c_iflag & IGNPAR)
416 up->port.ignore_status_mask |= UART_LSR_OE;
417 }
418
419 /*
420 * ignore all characters if CREAD is not set
421 */
422 if ((termios->c_cflag & CREAD) == 0)
423 up->port.ignore_status_mask |= UART_LSR_DR;
424
425 /*
426 * Modem status interrupts
427 */
428 up->ier &= ~UART_IER_MSI;
429 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
430 up->ier |= UART_IER_MSI;
431
432 up->lcr = cval;
433 /* Up to here it was mostly serial8250_do_set_termios() */
434
435 /*
436 * We enable TRIG_GRANU for RX and TX and additionally we set
437 * SCR_TX_EMPTY bit. The result is the following:
438 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
439 * - less than RX_TRIGGER number of bytes will also cause an interrupt
440 * once the UART decides that there no new bytes arriving.
441 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
442 * empty - the trigger level is ignored here.
443 *
444 * Once DMA is enabled:
445 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
446 * bytes in the TX FIFO. On each assert the DMA engine will move
447 * TX_TRIGGER bytes into the FIFO.
448 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
449 * the FIFO and move RX_TRIGGER bytes.
450 * This is because threshold and trigger values are the same.
451 */
452 up->fcr = UART_FCR_ENABLE_FIFO;
453 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
454 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
455
456 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
457 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
458
459 if (up->dma)
460 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
461 OMAP_UART_SCR_DMAMODE_CTL;
462
463 priv->xon = termios->c_cc[VSTART];
464 priv->xoff = termios->c_cc[VSTOP];
465
466 priv->efr = 0;
467 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
468
469 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
470 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
471 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
472 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
473 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
474 priv->efr |= UART_EFR_CTS;
475 } else if (up->port.flags & UPF_SOFT_FLOW) {
476 /*
477 * OMAP rx s/w flow control is borked; the transmitter remains
478 * stuck off even if rx flow control is subsequently disabled
479 */
480
481 /*
482 * IXOFF Flag:
483 * Enable XON/XOFF flow control on output.
484 * Transmit XON1, XOFF1
485 */
486 if (termios->c_iflag & IXOFF) {
487 up->port.status |= UPSTAT_AUTOXOFF;
488 priv->efr |= OMAP_UART_SW_TX;
489 }
490 }
491 omap8250_restore_regs(up);
492
493 spin_unlock_irq(&up->port.lock);
494 pm_runtime_mark_last_busy(port->dev);
495 pm_runtime_put_autosuspend(port->dev);
496
497 /* calculate wakeup latency constraint */
498 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
499 priv->latency = priv->calc_latency;
500
501 schedule_work(&priv->qos_work);
502
503 /* Don't rewrite B0 */
504 if (tty_termios_baud_rate(termios))
505 tty_termios_encode_baud_rate(termios, baud, baud);
506 }
507
508 /* same as 8250 except that we may have extra flow bits set in EFR */
omap_8250_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)509 static void omap_8250_pm(struct uart_port *port, unsigned int state,
510 unsigned int oldstate)
511 {
512 struct uart_8250_port *up = up_to_u8250p(port);
513 u8 efr;
514
515 pm_runtime_get_sync(port->dev);
516 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
517 efr = serial_in(up, UART_EFR);
518 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
519 serial_out(up, UART_LCR, 0);
520
521 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
522 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
523 serial_out(up, UART_EFR, efr);
524 serial_out(up, UART_LCR, 0);
525
526 pm_runtime_mark_last_busy(port->dev);
527 pm_runtime_put_autosuspend(port->dev);
528 }
529
omap_serial_fill_features_erratas(struct uart_8250_port * up,struct omap8250_priv * priv)530 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
531 struct omap8250_priv *priv)
532 {
533 static const struct soc_device_attribute k3_soc_devices[] = {
534 { .family = "AM65X", },
535 { .family = "J721E", .revision = "SR1.0" },
536 { /* sentinel */ }
537 };
538 u32 mvr, scheme;
539 u16 revision, major, minor;
540
541 mvr = uart_read(up, UART_OMAP_MVER);
542
543 /* Check revision register scheme */
544 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
545
546 switch (scheme) {
547 case 0: /* Legacy Scheme: OMAP2/3 */
548 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
549 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
550 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
551 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
552 break;
553 case 1:
554 /* New Scheme: OMAP4+ */
555 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
556 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
557 OMAP_UART_MVR_MAJ_SHIFT;
558 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
559 break;
560 default:
561 dev_warn(up->port.dev,
562 "Unknown revision, defaulting to highest\n");
563 /* highest possible revision */
564 major = 0xff;
565 minor = 0xff;
566 }
567 /* normalize revision for the driver */
568 revision = UART_BUILD_REVISION(major, minor);
569
570 switch (revision) {
571 case OMAP_UART_REV_46:
572 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
573 break;
574 case OMAP_UART_REV_52:
575 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
576 OMAP_UART_WER_HAS_TX_WAKEUP;
577 break;
578 case OMAP_UART_REV_63:
579 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
580 OMAP_UART_WER_HAS_TX_WAKEUP;
581 break;
582 default:
583 break;
584 }
585
586 /*
587 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
588 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
589 * to enable errata workaround.
590 */
591 if (soc_device_match(k3_soc_devices))
592 priv->habit &= ~UART_HAS_RHR_IT_DIS;
593 }
594
omap8250_uart_qos_work(struct work_struct * work)595 static void omap8250_uart_qos_work(struct work_struct *work)
596 {
597 struct omap8250_priv *priv;
598
599 priv = container_of(work, struct omap8250_priv, qos_work);
600 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
601 }
602
603 #ifdef CONFIG_SERIAL_8250_DMA
604 static int omap_8250_dma_handle_irq(struct uart_port *port);
605 #endif
606
omap8250_irq(int irq,void * dev_id)607 static irqreturn_t omap8250_irq(int irq, void *dev_id)
608 {
609 struct uart_port *port = dev_id;
610 struct omap8250_priv *priv = port->private_data;
611 struct uart_8250_port *up = up_to_u8250p(port);
612 unsigned int iir, lsr;
613 int ret;
614
615 #ifdef CONFIG_SERIAL_8250_DMA
616 if (up->dma) {
617 ret = omap_8250_dma_handle_irq(port);
618 return IRQ_RETVAL(ret);
619 }
620 #endif
621
622 serial8250_rpm_get(up);
623 lsr = serial_port_in(port, UART_LSR);
624 iir = serial_port_in(port, UART_IIR);
625 ret = serial8250_handle_irq(port, iir);
626
627 /*
628 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
629 * FIFO has been drained, in which case a dummy read of RX FIFO
630 * is required to clear RX TIMEOUT condition.
631 */
632 if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
633 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
634 serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
635 serial_port_in(port, UART_RX);
636 }
637
638 /* Stop processing interrupts on input overrun */
639 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
640 unsigned long delay;
641
642 up->ier = port->serial_in(port, UART_IER);
643 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
644 port->ops->stop_rx(port);
645 } else {
646 /* Keep restarting the timer until
647 * the input overrun subsides.
648 */
649 cancel_delayed_work(&up->overrun_backoff);
650 }
651
652 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
653 schedule_delayed_work(&up->overrun_backoff, delay);
654 }
655
656 serial8250_rpm_put(up);
657
658 return IRQ_RETVAL(ret);
659 }
660
omap_8250_startup(struct uart_port * port)661 static int omap_8250_startup(struct uart_port *port)
662 {
663 struct uart_8250_port *up = up_to_u8250p(port);
664 struct omap8250_priv *priv = port->private_data;
665 int ret;
666
667 if (priv->wakeirq) {
668 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
669 if (ret)
670 return ret;
671 }
672
673 pm_runtime_get_sync(port->dev);
674
675 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
676
677 serial_out(up, UART_LCR, UART_LCR_WLEN8);
678
679 up->lsr_saved_flags = 0;
680 up->msr_saved_flags = 0;
681
682 /* Disable DMA for console UART */
683 if (uart_console(port))
684 up->dma = NULL;
685
686 if (up->dma) {
687 ret = serial8250_request_dma(up);
688 if (ret) {
689 dev_warn_ratelimited(port->dev,
690 "failed to request DMA\n");
691 up->dma = NULL;
692 }
693 }
694
695 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
696 dev_name(port->dev), port);
697 if (ret < 0)
698 goto err;
699
700 up->ier = UART_IER_RLSI | UART_IER_RDI;
701 serial_out(up, UART_IER, up->ier);
702
703 #ifdef CONFIG_PM
704 up->capabilities |= UART_CAP_RPM;
705 #endif
706
707 /* Enable module level wake up */
708 priv->wer = OMAP_UART_WER_MOD_WKUP;
709 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
710 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
711 serial_out(up, UART_OMAP_WER, priv->wer);
712
713 if (up->dma && !(priv->habit & UART_HAS_EFR2))
714 up->dma->rx_dma(up);
715
716 pm_runtime_mark_last_busy(port->dev);
717 pm_runtime_put_autosuspend(port->dev);
718 return 0;
719 err:
720 pm_runtime_mark_last_busy(port->dev);
721 pm_runtime_put_autosuspend(port->dev);
722 dev_pm_clear_wake_irq(port->dev);
723 return ret;
724 }
725
omap_8250_shutdown(struct uart_port * port)726 static void omap_8250_shutdown(struct uart_port *port)
727 {
728 struct uart_8250_port *up = up_to_u8250p(port);
729 struct omap8250_priv *priv = port->private_data;
730
731 flush_work(&priv->qos_work);
732 if (up->dma)
733 omap_8250_rx_dma_flush(up);
734
735 pm_runtime_get_sync(port->dev);
736
737 serial_out(up, UART_OMAP_WER, 0);
738 if (priv->habit & UART_HAS_EFR2)
739 serial_out(up, UART_OMAP_EFR2, 0x0);
740
741 up->ier = 0;
742 serial_out(up, UART_IER, 0);
743
744 if (up->dma)
745 serial8250_release_dma(up);
746
747 /*
748 * Disable break condition and FIFOs
749 */
750 if (up->lcr & UART_LCR_SBC)
751 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
752 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
753
754 pm_runtime_mark_last_busy(port->dev);
755 pm_runtime_put_autosuspend(port->dev);
756 free_irq(port->irq, port);
757 dev_pm_clear_wake_irq(port->dev);
758 }
759
omap_8250_throttle(struct uart_port * port)760 static void omap_8250_throttle(struct uart_port *port)
761 {
762 struct omap8250_priv *priv = port->private_data;
763 unsigned long flags;
764
765 pm_runtime_get_sync(port->dev);
766
767 spin_lock_irqsave(&port->lock, flags);
768 port->ops->stop_rx(port);
769 priv->throttled = true;
770 spin_unlock_irqrestore(&port->lock, flags);
771
772 pm_runtime_mark_last_busy(port->dev);
773 pm_runtime_put_autosuspend(port->dev);
774 }
775
omap_8250_unthrottle(struct uart_port * port)776 static void omap_8250_unthrottle(struct uart_port *port)
777 {
778 struct omap8250_priv *priv = port->private_data;
779 struct uart_8250_port *up = up_to_u8250p(port);
780 unsigned long flags;
781
782 pm_runtime_get_sync(port->dev);
783
784 spin_lock_irqsave(&port->lock, flags);
785 priv->throttled = false;
786 if (up->dma)
787 up->dma->rx_dma(up);
788 up->ier |= UART_IER_RLSI | UART_IER_RDI;
789 port->read_status_mask |= UART_LSR_DR;
790 serial_out(up, UART_IER, up->ier);
791 spin_unlock_irqrestore(&port->lock, flags);
792
793 pm_runtime_mark_last_busy(port->dev);
794 pm_runtime_put_autosuspend(port->dev);
795 }
796
797 #ifdef CONFIG_SERIAL_8250_DMA
798 static int omap_8250_rx_dma(struct uart_8250_port *p);
799
800 /* Must be called while priv->rx_dma_lock is held */
__dma_rx_do_complete(struct uart_8250_port * p)801 static void __dma_rx_do_complete(struct uart_8250_port *p)
802 {
803 struct uart_8250_dma *dma = p->dma;
804 struct tty_port *tty_port = &p->port.state->port;
805 struct omap8250_priv *priv = p->port.private_data;
806 struct dma_chan *rxchan = dma->rxchan;
807 dma_cookie_t cookie;
808 struct dma_tx_state state;
809 int count;
810 int ret;
811 u32 reg;
812
813 if (!dma->rx_running)
814 goto out;
815
816 cookie = dma->rx_cookie;
817 dma->rx_running = 0;
818
819 /* Re-enable RX FIFO interrupt now that transfer is complete */
820 if (priv->habit & UART_HAS_RHR_IT_DIS) {
821 reg = serial_in(p, UART_OMAP_IER2);
822 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
823 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
824 }
825
826 dmaengine_tx_status(rxchan, cookie, &state);
827
828 count = dma->rx_size - state.residue + state.in_flight_bytes;
829 if (count < dma->rx_size) {
830 dmaengine_terminate_async(rxchan);
831
832 /*
833 * Poll for teardown to complete which guarantees in
834 * flight data is drained.
835 */
836 if (state.in_flight_bytes) {
837 int poll_count = 25;
838
839 while (dmaengine_tx_status(rxchan, cookie, NULL) &&
840 poll_count--)
841 cpu_relax();
842
843 if (poll_count == -1)
844 dev_err(p->port.dev, "teardown incomplete\n");
845 }
846 }
847 if (!count)
848 goto out;
849 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
850
851 p->port.icount.rx += ret;
852 p->port.icount.buf_overrun += count - ret;
853 out:
854
855 tty_flip_buffer_push(tty_port);
856 }
857
__dma_rx_complete(void * param)858 static void __dma_rx_complete(void *param)
859 {
860 struct uart_8250_port *p = param;
861 struct omap8250_priv *priv = p->port.private_data;
862 struct uart_8250_dma *dma = p->dma;
863 struct dma_tx_state state;
864 unsigned long flags;
865
866 spin_lock_irqsave(&p->port.lock, flags);
867
868 /*
869 * If the tx status is not DMA_COMPLETE, then this is a delayed
870 * completion callback. A previous RX timeout flush would have
871 * already pushed the data, so exit.
872 */
873 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
874 DMA_COMPLETE) {
875 spin_unlock_irqrestore(&p->port.lock, flags);
876 return;
877 }
878 __dma_rx_do_complete(p);
879 if (!priv->throttled) {
880 p->ier |= UART_IER_RLSI | UART_IER_RDI;
881 serial_out(p, UART_IER, p->ier);
882 if (!(priv->habit & UART_HAS_EFR2))
883 omap_8250_rx_dma(p);
884 }
885
886 spin_unlock_irqrestore(&p->port.lock, flags);
887 }
888
omap_8250_rx_dma_flush(struct uart_8250_port * p)889 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
890 {
891 struct omap8250_priv *priv = p->port.private_data;
892 struct uart_8250_dma *dma = p->dma;
893 struct dma_tx_state state;
894 unsigned long flags;
895 int ret;
896
897 spin_lock_irqsave(&priv->rx_dma_lock, flags);
898
899 if (!dma->rx_running) {
900 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
901 return;
902 }
903
904 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
905 if (ret == DMA_IN_PROGRESS) {
906 ret = dmaengine_pause(dma->rxchan);
907 if (WARN_ON_ONCE(ret))
908 priv->rx_dma_broken = true;
909 }
910 __dma_rx_do_complete(p);
911 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
912 }
913
omap_8250_rx_dma(struct uart_8250_port * p)914 static int omap_8250_rx_dma(struct uart_8250_port *p)
915 {
916 struct omap8250_priv *priv = p->port.private_data;
917 struct uart_8250_dma *dma = p->dma;
918 int err = 0;
919 struct dma_async_tx_descriptor *desc;
920 unsigned long flags;
921 u32 reg;
922
923 if (priv->rx_dma_broken)
924 return -EINVAL;
925
926 spin_lock_irqsave(&priv->rx_dma_lock, flags);
927
928 if (dma->rx_running) {
929 enum dma_status state;
930
931 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
932 if (state == DMA_COMPLETE) {
933 /*
934 * Disable RX interrupts to allow RX DMA completion
935 * callback to run.
936 */
937 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
938 serial_out(p, UART_IER, p->ier);
939 }
940 goto out;
941 }
942
943 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
944 dma->rx_size, DMA_DEV_TO_MEM,
945 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
946 if (!desc) {
947 err = -EBUSY;
948 goto out;
949 }
950
951 dma->rx_running = 1;
952 desc->callback = __dma_rx_complete;
953 desc->callback_param = p;
954
955 dma->rx_cookie = dmaengine_submit(desc);
956
957 /*
958 * Disable RX FIFO interrupt while RX DMA is enabled, else
959 * spurious interrupt may be raised when data is in the RX FIFO
960 * but is yet to be drained by DMA.
961 */
962 if (priv->habit & UART_HAS_RHR_IT_DIS) {
963 reg = serial_in(p, UART_OMAP_IER2);
964 reg |= UART_OMAP_IER2_RHR_IT_DIS;
965 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
966 }
967
968 dma_async_issue_pending(dma->rxchan);
969 out:
970 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
971 return err;
972 }
973
974 static int omap_8250_tx_dma(struct uart_8250_port *p);
975
omap_8250_dma_tx_complete(void * param)976 static void omap_8250_dma_tx_complete(void *param)
977 {
978 struct uart_8250_port *p = param;
979 struct uart_8250_dma *dma = p->dma;
980 struct circ_buf *xmit = &p->port.state->xmit;
981 unsigned long flags;
982 bool en_thri = false;
983 struct omap8250_priv *priv = p->port.private_data;
984
985 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
986 UART_XMIT_SIZE, DMA_TO_DEVICE);
987
988 spin_lock_irqsave(&p->port.lock, flags);
989
990 dma->tx_running = 0;
991
992 uart_xmit_advance(&p->port, dma->tx_size);
993
994 if (priv->delayed_restore) {
995 priv->delayed_restore = 0;
996 omap8250_restore_regs(p);
997 }
998
999 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1000 uart_write_wakeup(&p->port);
1001
1002 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1003 int ret;
1004
1005 ret = omap_8250_tx_dma(p);
1006 if (ret)
1007 en_thri = true;
1008 } else if (p->capabilities & UART_CAP_RPM) {
1009 en_thri = true;
1010 }
1011
1012 if (en_thri) {
1013 dma->tx_err = 1;
1014 serial8250_set_THRI(p);
1015 }
1016
1017 spin_unlock_irqrestore(&p->port.lock, flags);
1018 }
1019
omap_8250_tx_dma(struct uart_8250_port * p)1020 static int omap_8250_tx_dma(struct uart_8250_port *p)
1021 {
1022 struct uart_8250_dma *dma = p->dma;
1023 struct omap8250_priv *priv = p->port.private_data;
1024 struct circ_buf *xmit = &p->port.state->xmit;
1025 struct dma_async_tx_descriptor *desc;
1026 unsigned int skip_byte = 0;
1027 int ret;
1028
1029 if (dma->tx_running)
1030 return 0;
1031 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1032
1033 /*
1034 * Even if no data, we need to return an error for the two cases
1035 * below so serial8250_tx_chars() is invoked and properly clears
1036 * THRI and/or runtime suspend.
1037 */
1038 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1039 ret = -EBUSY;
1040 goto err;
1041 }
1042 serial8250_clear_THRI(p);
1043 return 0;
1044 }
1045
1046 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1047 if (priv->habit & OMAP_DMA_TX_KICK) {
1048 u8 tx_lvl;
1049
1050 /*
1051 * We need to put the first byte into the FIFO in order to start
1052 * the DMA transfer. For transfers smaller than four bytes we
1053 * don't bother doing DMA at all. It seem not matter if there
1054 * are still bytes in the FIFO from the last transfer (in case
1055 * we got here directly from omap_8250_dma_tx_complete()). Bytes
1056 * leaving the FIFO seem not to trigger the DMA transfer. It is
1057 * really the byte that we put into the FIFO.
1058 * If the FIFO is already full then we most likely got here from
1059 * omap_8250_dma_tx_complete(). And this means the DMA engine
1060 * just completed its work. We don't have to wait the complete
1061 * 86us at 115200,8n1 but around 60us (not to mention lower
1062 * baudrates). So in that case we take the interrupt and try
1063 * again with an empty FIFO.
1064 */
1065 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1066 if (tx_lvl == p->tx_loadsz) {
1067 ret = -EBUSY;
1068 goto err;
1069 }
1070 if (dma->tx_size < 4) {
1071 ret = -EINVAL;
1072 goto err;
1073 }
1074 skip_byte = 1;
1075 }
1076
1077 desc = dmaengine_prep_slave_single(dma->txchan,
1078 dma->tx_addr + xmit->tail + skip_byte,
1079 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1080 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1081 if (!desc) {
1082 ret = -EBUSY;
1083 goto err;
1084 }
1085
1086 dma->tx_running = 1;
1087
1088 desc->callback = omap_8250_dma_tx_complete;
1089 desc->callback_param = p;
1090
1091 dma->tx_cookie = dmaengine_submit(desc);
1092
1093 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1094 UART_XMIT_SIZE, DMA_TO_DEVICE);
1095
1096 dma_async_issue_pending(dma->txchan);
1097 if (dma->tx_err)
1098 dma->tx_err = 0;
1099
1100 serial8250_clear_THRI(p);
1101 if (skip_byte)
1102 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1103 return 0;
1104 err:
1105 dma->tx_err = 1;
1106 return ret;
1107 }
1108
handle_rx_dma(struct uart_8250_port * up,unsigned int iir)1109 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1110 {
1111 switch (iir & 0x3f) {
1112 case UART_IIR_RLSI:
1113 case UART_IIR_RX_TIMEOUT:
1114 case UART_IIR_RDI:
1115 omap_8250_rx_dma_flush(up);
1116 return true;
1117 }
1118 return omap_8250_rx_dma(up);
1119 }
1120
omap_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,u16 status)1121 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1122 {
1123 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1124 (iir & UART_IIR_RDI)) {
1125 if (handle_rx_dma(up, iir)) {
1126 status = serial8250_rx_chars(up, status);
1127 omap_8250_rx_dma(up);
1128 }
1129 }
1130
1131 return status;
1132 }
1133
am654_8250_handle_rx_dma(struct uart_8250_port * up,u8 iir,u16 status)1134 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1135 u16 status)
1136 {
1137 /*
1138 * Queue a new transfer if FIFO has data.
1139 */
1140 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1141 (up->ier & UART_IER_RDI)) {
1142 omap_8250_rx_dma(up);
1143 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1144 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1145 /*
1146 * Disable RX timeout, read IIR to clear
1147 * current timeout condition, clear EFR2 to
1148 * periodic timeouts, re-enable interrupts.
1149 */
1150 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1151 serial_out(up, UART_IER, up->ier);
1152 omap_8250_rx_dma_flush(up);
1153 serial_in(up, UART_IIR);
1154 serial_out(up, UART_OMAP_EFR2, 0x0);
1155 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1156 serial_out(up, UART_IER, up->ier);
1157 }
1158 }
1159
1160 /*
1161 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1162 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1163 * use the default routine in the non-DMA case and this one for with DMA.
1164 */
omap_8250_dma_handle_irq(struct uart_port * port)1165 static int omap_8250_dma_handle_irq(struct uart_port *port)
1166 {
1167 struct uart_8250_port *up = up_to_u8250p(port);
1168 struct omap8250_priv *priv = up->port.private_data;
1169 u16 status;
1170 u8 iir;
1171
1172 serial8250_rpm_get(up);
1173
1174 iir = serial_port_in(port, UART_IIR);
1175 if (iir & UART_IIR_NO_INT) {
1176 serial8250_rpm_put(up);
1177 return IRQ_HANDLED;
1178 }
1179
1180 spin_lock(&port->lock);
1181
1182 status = serial_port_in(port, UART_LSR);
1183
1184 if (priv->habit & UART_HAS_EFR2)
1185 am654_8250_handle_rx_dma(up, iir, status);
1186 else
1187 status = omap_8250_handle_rx_dma(up, iir, status);
1188
1189 serial8250_modem_status(up);
1190 if (status & UART_LSR_THRE && up->dma->tx_err) {
1191 if (uart_tx_stopped(&up->port) ||
1192 uart_circ_empty(&up->port.state->xmit)) {
1193 up->dma->tx_err = 0;
1194 serial8250_tx_chars(up);
1195 } else {
1196 /*
1197 * try again due to an earlier failer which
1198 * might have been resolved by now.
1199 */
1200 if (omap_8250_tx_dma(up))
1201 serial8250_tx_chars(up);
1202 }
1203 }
1204
1205 uart_unlock_and_check_sysrq(port);
1206
1207 serial8250_rpm_put(up);
1208 return 1;
1209 }
1210
the_no_dma_filter_fn(struct dma_chan * chan,void * param)1211 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1212 {
1213 return false;
1214 }
1215
1216 #else
1217
omap_8250_rx_dma(struct uart_8250_port * p)1218 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1219 {
1220 return -EINVAL;
1221 }
1222 #endif
1223
omap8250_no_handle_irq(struct uart_port * port)1224 static int omap8250_no_handle_irq(struct uart_port *port)
1225 {
1226 /* IRQ has not been requested but handling irq? */
1227 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1228 return 0;
1229 }
1230
1231 static struct omap8250_dma_params am654_dma = {
1232 .rx_size = SZ_2K,
1233 .rx_trigger = 1,
1234 .tx_trigger = TX_TRIGGER,
1235 };
1236
1237 static struct omap8250_dma_params am33xx_dma = {
1238 .rx_size = RX_TRIGGER,
1239 .rx_trigger = RX_TRIGGER,
1240 .tx_trigger = TX_TRIGGER,
1241 };
1242
1243 static struct omap8250_platdata am654_platdata = {
1244 .dma_params = &am654_dma,
1245 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1246 UART_RX_TIMEOUT_QUIRK,
1247 };
1248
1249 static struct omap8250_platdata am33xx_platdata = {
1250 .dma_params = &am33xx_dma,
1251 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1252 };
1253
1254 static struct omap8250_platdata omap4_platdata = {
1255 .dma_params = &am33xx_dma,
1256 .habit = UART_ERRATA_CLOCK_DISABLE,
1257 };
1258
1259 static const struct of_device_id omap8250_dt_ids[] = {
1260 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1261 { .compatible = "ti,omap2-uart" },
1262 { .compatible = "ti,omap3-uart" },
1263 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1264 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1265 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1266 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1267 {},
1268 };
1269 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1270
omap8250_probe(struct platform_device * pdev)1271 static int omap8250_probe(struct platform_device *pdev)
1272 {
1273 struct device_node *np = pdev->dev.of_node;
1274 struct omap8250_priv *priv;
1275 const struct omap8250_platdata *pdata;
1276 struct uart_8250_port up;
1277 struct resource *regs;
1278 void __iomem *membase;
1279 int irq, ret;
1280
1281 irq = platform_get_irq(pdev, 0);
1282 if (irq < 0)
1283 return irq;
1284
1285 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1286 if (!regs) {
1287 dev_err(&pdev->dev, "missing registers\n");
1288 return -EINVAL;
1289 }
1290
1291 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1292 if (!priv)
1293 return -ENOMEM;
1294
1295 membase = devm_ioremap(&pdev->dev, regs->start,
1296 resource_size(regs));
1297 if (!membase)
1298 return -ENODEV;
1299
1300 memset(&up, 0, sizeof(up));
1301 up.port.dev = &pdev->dev;
1302 up.port.mapbase = regs->start;
1303 up.port.membase = membase;
1304 up.port.irq = irq;
1305 /*
1306 * It claims to be 16C750 compatible however it is a little different.
1307 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1308 * have) is enabled via EFR instead of MCR. The type is set here 8250
1309 * just to get things going. UNKNOWN does not work for a few reasons and
1310 * we don't need our own type since we don't use 8250's set_termios()
1311 * or pm callback.
1312 */
1313 up.port.type = PORT_8250;
1314 up.port.iotype = UPIO_MEM;
1315 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1316 UPF_HARD_FLOW;
1317 up.port.private_data = priv;
1318
1319 up.port.regshift = 2;
1320 up.port.fifosize = 64;
1321 up.tx_loadsz = 64;
1322 up.capabilities = UART_CAP_FIFO;
1323 #ifdef CONFIG_PM
1324 /*
1325 * Runtime PM is mostly transparent. However to do it right we need to a
1326 * TX empty interrupt before we can put the device to auto idle. So if
1327 * PM is not enabled we don't add that flag and can spare that one extra
1328 * interrupt in the TX path.
1329 */
1330 up.capabilities |= UART_CAP_RPM;
1331 #endif
1332 up.port.set_termios = omap_8250_set_termios;
1333 up.port.set_mctrl = omap8250_set_mctrl;
1334 up.port.pm = omap_8250_pm;
1335 up.port.startup = omap_8250_startup;
1336 up.port.shutdown = omap_8250_shutdown;
1337 up.port.throttle = omap_8250_throttle;
1338 up.port.unthrottle = omap_8250_unthrottle;
1339 up.port.rs485_config = serial8250_em485_config;
1340 up.port.rs485_supported = serial8250_em485_supported;
1341 up.rs485_start_tx = serial8250_em485_start_tx;
1342 up.rs485_stop_tx = serial8250_em485_stop_tx;
1343 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1344
1345 ret = of_alias_get_id(np, "serial");
1346 if (ret < 0) {
1347 dev_err(&pdev->dev, "failed to get alias\n");
1348 return ret;
1349 }
1350 up.port.line = ret;
1351
1352 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1353 struct clk *clk;
1354
1355 clk = devm_clk_get(&pdev->dev, NULL);
1356 if (IS_ERR(clk)) {
1357 if (PTR_ERR(clk) == -EPROBE_DEFER)
1358 return -EPROBE_DEFER;
1359 } else {
1360 up.port.uartclk = clk_get_rate(clk);
1361 }
1362 }
1363
1364 if (of_property_read_u32(np, "overrun-throttle-ms",
1365 &up.overrun_backoff_time_ms) != 0)
1366 up.overrun_backoff_time_ms = 0;
1367
1368 priv->wakeirq = irq_of_parse_and_map(np, 1);
1369
1370 pdata = of_device_get_match_data(&pdev->dev);
1371 if (pdata)
1372 priv->habit |= pdata->habit;
1373
1374 if (!up.port.uartclk) {
1375 up.port.uartclk = DEFAULT_CLK_SPEED;
1376 dev_warn(&pdev->dev,
1377 "No clock speed specified: using default: %d\n",
1378 DEFAULT_CLK_SPEED);
1379 }
1380
1381 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1382 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1383 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1384 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1385
1386 spin_lock_init(&priv->rx_dma_lock);
1387
1388 device_init_wakeup(&pdev->dev, true);
1389 pm_runtime_enable(&pdev->dev);
1390 pm_runtime_use_autosuspend(&pdev->dev);
1391
1392 /*
1393 * Disable runtime PM until autosuspend delay unless specifically
1394 * enabled by the user via sysfs. This is the historic way to
1395 * prevent an unsafe default policy with lossy characters on wake-up.
1396 * For serdev devices this is not needed, the policy can be managed by
1397 * the serdev driver.
1398 */
1399 if (!of_get_available_child_count(pdev->dev.of_node))
1400 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1401
1402 pm_runtime_irq_safe(&pdev->dev);
1403
1404 pm_runtime_get_sync(&pdev->dev);
1405
1406 omap_serial_fill_features_erratas(&up, priv);
1407 up.port.handle_irq = omap8250_no_handle_irq;
1408 priv->rx_trigger = RX_TRIGGER;
1409 priv->tx_trigger = TX_TRIGGER;
1410 #ifdef CONFIG_SERIAL_8250_DMA
1411 /*
1412 * Oh DMA support. If there are no DMA properties in the DT then
1413 * we will fall back to a generic DMA channel which does not
1414 * really work here. To ensure that we do not get a generic DMA
1415 * channel assigned, we have the the_no_dma_filter_fn() here.
1416 * To avoid "failed to request DMA" messages we check for DMA
1417 * properties in DT.
1418 */
1419 ret = of_property_count_strings(np, "dma-names");
1420 if (ret == 2) {
1421 struct omap8250_dma_params *dma_params = NULL;
1422
1423 up.dma = &priv->omap8250_dma;
1424 up.dma->fn = the_no_dma_filter_fn;
1425 up.dma->tx_dma = omap_8250_tx_dma;
1426 up.dma->rx_dma = omap_8250_rx_dma;
1427 if (pdata)
1428 dma_params = pdata->dma_params;
1429
1430 if (dma_params) {
1431 up.dma->rx_size = dma_params->rx_size;
1432 up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1433 up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1434 priv->rx_trigger = dma_params->rx_trigger;
1435 priv->tx_trigger = dma_params->tx_trigger;
1436 } else {
1437 up.dma->rx_size = RX_TRIGGER;
1438 up.dma->rxconf.src_maxburst = RX_TRIGGER;
1439 up.dma->txconf.dst_maxburst = TX_TRIGGER;
1440 }
1441 }
1442 #endif
1443 ret = serial8250_register_8250_port(&up);
1444 if (ret < 0) {
1445 dev_err(&pdev->dev, "unable to register 8250 port\n");
1446 goto err;
1447 }
1448 priv->line = ret;
1449 platform_set_drvdata(pdev, priv);
1450 pm_runtime_mark_last_busy(&pdev->dev);
1451 pm_runtime_put_autosuspend(&pdev->dev);
1452 return 0;
1453 err:
1454 pm_runtime_dont_use_autosuspend(&pdev->dev);
1455 pm_runtime_put_sync(&pdev->dev);
1456 pm_runtime_disable(&pdev->dev);
1457 return ret;
1458 }
1459
omap8250_remove(struct platform_device * pdev)1460 static int omap8250_remove(struct platform_device *pdev)
1461 {
1462 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1463 int err;
1464
1465 err = pm_runtime_resume_and_get(&pdev->dev);
1466 if (err)
1467 return err;
1468
1469 pm_runtime_dont_use_autosuspend(&pdev->dev);
1470 pm_runtime_put_sync(&pdev->dev);
1471 flush_work(&priv->qos_work);
1472 pm_runtime_disable(&pdev->dev);
1473 serial8250_unregister_port(priv->line);
1474 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1475 device_init_wakeup(&pdev->dev, false);
1476 return 0;
1477 }
1478
1479 #ifdef CONFIG_PM_SLEEP
omap8250_prepare(struct device * dev)1480 static int omap8250_prepare(struct device *dev)
1481 {
1482 struct omap8250_priv *priv = dev_get_drvdata(dev);
1483
1484 if (!priv)
1485 return 0;
1486 priv->is_suspending = true;
1487 return 0;
1488 }
1489
omap8250_complete(struct device * dev)1490 static void omap8250_complete(struct device *dev)
1491 {
1492 struct omap8250_priv *priv = dev_get_drvdata(dev);
1493
1494 if (!priv)
1495 return;
1496 priv->is_suspending = false;
1497 }
1498
omap8250_suspend(struct device * dev)1499 static int omap8250_suspend(struct device *dev)
1500 {
1501 struct omap8250_priv *priv = dev_get_drvdata(dev);
1502 struct uart_8250_port *up = serial8250_get_port(priv->line);
1503
1504 serial8250_suspend_port(priv->line);
1505
1506 pm_runtime_get_sync(dev);
1507 if (!device_may_wakeup(dev))
1508 priv->wer = 0;
1509 serial_out(up, UART_OMAP_WER, priv->wer);
1510 pm_runtime_mark_last_busy(dev);
1511 pm_runtime_put_autosuspend(dev);
1512
1513 flush_work(&priv->qos_work);
1514 return 0;
1515 }
1516
omap8250_resume(struct device * dev)1517 static int omap8250_resume(struct device *dev)
1518 {
1519 struct omap8250_priv *priv = dev_get_drvdata(dev);
1520
1521 serial8250_resume_port(priv->line);
1522 return 0;
1523 }
1524 #else
1525 #define omap8250_prepare NULL
1526 #define omap8250_complete NULL
1527 #endif
1528
1529 #ifdef CONFIG_PM
omap8250_lost_context(struct uart_8250_port * up)1530 static int omap8250_lost_context(struct uart_8250_port *up)
1531 {
1532 u32 val;
1533
1534 val = serial_in(up, UART_OMAP_SCR);
1535 /*
1536 * If we lose context, then SCR is set to its reset value of zero.
1537 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1538 * among other bits, to never set the register back to zero again.
1539 */
1540 if (!val)
1541 return 1;
1542 return 0;
1543 }
1544
1545 /* TODO: in future, this should happen via API in drivers/reset/ */
omap8250_soft_reset(struct device * dev)1546 static int omap8250_soft_reset(struct device *dev)
1547 {
1548 struct omap8250_priv *priv = dev_get_drvdata(dev);
1549 struct uart_8250_port *up = serial8250_get_port(priv->line);
1550 int timeout = 100;
1551 int sysc;
1552 int syss;
1553
1554 /*
1555 * At least on omap4, unused uarts may not idle after reset without
1556 * a basic scr dma configuration even with no dma in use. The
1557 * module clkctrl status bits will be 1 instead of 3 blocking idle
1558 * for the whole clockdomain. The softreset below will clear scr,
1559 * and we restore it on resume so this is safe to do on all SoCs
1560 * needing omap8250_soft_reset() quirk. Do it in two writes as
1561 * recommended in the comment for omap8250_update_scr().
1562 */
1563 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1564 serial_out(up, UART_OMAP_SCR,
1565 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1566
1567 sysc = serial_in(up, UART_OMAP_SYSC);
1568
1569 /* softreset the UART */
1570 sysc |= OMAP_UART_SYSC_SOFTRESET;
1571 serial_out(up, UART_OMAP_SYSC, sysc);
1572
1573 /* By experiments, 1us enough for reset complete on AM335x */
1574 do {
1575 udelay(1);
1576 syss = serial_in(up, UART_OMAP_SYSS);
1577 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1578
1579 if (!timeout) {
1580 dev_err(dev, "timed out waiting for reset done\n");
1581 return -ETIMEDOUT;
1582 }
1583
1584 return 0;
1585 }
1586
omap8250_runtime_suspend(struct device * dev)1587 static int omap8250_runtime_suspend(struct device *dev)
1588 {
1589 struct omap8250_priv *priv = dev_get_drvdata(dev);
1590 struct uart_8250_port *up;
1591
1592 /* In case runtime-pm tries this before we are setup */
1593 if (!priv)
1594 return 0;
1595
1596 up = serial8250_get_port(priv->line);
1597 /*
1598 * When using 'no_console_suspend', the console UART must not be
1599 * suspended. Since driver suspend is managed by runtime suspend,
1600 * preventing runtime suspend (by returning error) will keep device
1601 * active during suspend.
1602 */
1603 if (priv->is_suspending && !console_suspend_enabled) {
1604 if (uart_console(&up->port))
1605 return -EBUSY;
1606 }
1607
1608 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1609 int ret;
1610
1611 ret = omap8250_soft_reset(dev);
1612 if (ret)
1613 return ret;
1614
1615 /* Restore to UART mode after reset (for wakeup) */
1616 omap8250_update_mdr1(up, priv);
1617 /* Restore wakeup enable register */
1618 serial_out(up, UART_OMAP_WER, priv->wer);
1619 }
1620
1621 if (up->dma && up->dma->rxchan)
1622 omap_8250_rx_dma_flush(up);
1623
1624 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1625 schedule_work(&priv->qos_work);
1626
1627 return 0;
1628 }
1629
omap8250_runtime_resume(struct device * dev)1630 static int omap8250_runtime_resume(struct device *dev)
1631 {
1632 struct omap8250_priv *priv = dev_get_drvdata(dev);
1633 struct uart_8250_port *up;
1634
1635 /* In case runtime-pm tries this before we are setup */
1636 if (!priv)
1637 return 0;
1638
1639 up = serial8250_get_port(priv->line);
1640
1641 if (omap8250_lost_context(up))
1642 omap8250_restore_regs(up);
1643
1644 if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1645 omap_8250_rx_dma(up);
1646
1647 priv->latency = priv->calc_latency;
1648 schedule_work(&priv->qos_work);
1649 return 0;
1650 }
1651 #endif
1652
1653 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
omap8250_console_fixup(void)1654 static int __init omap8250_console_fixup(void)
1655 {
1656 char *omap_str;
1657 char *options;
1658 u8 idx;
1659
1660 if (strstr(boot_command_line, "console=ttyS"))
1661 /* user set a ttyS based name for the console */
1662 return 0;
1663
1664 omap_str = strstr(boot_command_line, "console=ttyO");
1665 if (!omap_str)
1666 /* user did not set ttyO based console, so we don't care */
1667 return 0;
1668
1669 omap_str += 12;
1670 if ('0' <= *omap_str && *omap_str <= '9')
1671 idx = *omap_str - '0';
1672 else
1673 return 0;
1674
1675 omap_str++;
1676 if (omap_str[0] == ',') {
1677 omap_str++;
1678 options = omap_str;
1679 } else {
1680 options = NULL;
1681 }
1682
1683 add_preferred_console("ttyS", idx, options);
1684 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1685 idx, idx);
1686 pr_err("This ensures that you still see kernel messages. Please\n");
1687 pr_err("update your kernel commandline.\n");
1688 return 0;
1689 }
1690 console_initcall(omap8250_console_fixup);
1691 #endif
1692
1693 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1694 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1695 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1696 omap8250_runtime_resume, NULL)
1697 .prepare = omap8250_prepare,
1698 .complete = omap8250_complete,
1699 };
1700
1701 static struct platform_driver omap8250_platform_driver = {
1702 .driver = {
1703 .name = "omap8250",
1704 .pm = &omap8250_dev_pm_ops,
1705 .of_match_table = omap8250_dt_ids,
1706 },
1707 .probe = omap8250_probe,
1708 .remove = omap8250_remove,
1709 };
1710 module_platform_driver(omap8250_platform_driver);
1711
1712 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1713 MODULE_DESCRIPTION("OMAP 8250 Driver");
1714 MODULE_LICENSE("GPL v2");
1715
