| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ids.c | 186 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
202 struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? in amdgpu_vmid_grab_idle()
213 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
214 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
277 if (adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_reserved()
323 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
349 if (needs_flush && !adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_used()
385 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
444 id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
471 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_free_reserved()
[all …]
|
| D | amdgpu_vm.c | 126 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid)); in amdgpu_vm_set_pasid()
134 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm, in amdgpu_vm_set_pasid()
465 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
504 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
1013 vram_base = bo_adev->vm_manager.vram_base_offset; in amdgpu_vm_bo_update()
1096 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); in amdgpu_vm_update_prt_state()
1097 enable = !!atomic_read(&adev->vm_manager.num_prt_users); in amdgpu_vm_update_prt_state()
1099 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); in amdgpu_vm_update_prt_state()
1112 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) in amdgpu_vm_prt_get()
1123 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) in amdgpu_vm_prt_put()
[all …]
|
| D | amdgpu_vm_pt.c | 57 adev->vm_manager.block_size; in amdgpu_vm_pt_level_shift()
79 shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_pt_num_entries()
80 if (level == adev->vm_manager.root_level) in amdgpu_vm_pt_num_entries()
82 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_pt_num_entries()
104 shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_pt_num_ats_entries()
120 if (level <= adev->vm_manager.root_level) in amdgpu_vm_pt_entries_mask()
179 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
378 unsigned int level = adev->vm_manager.root_level; in amdgpu_vm_pt_clear()
734 enum amdgpu_vm_level root = adev->vm_manager.root_level; in amdgpu_vm_pt_is_root_clean()
765 level += params->adev->vm_manager.root_level; in amdgpu_vm_pde_update()
[all …]
|
| D | gfxhub_v3_0_3.c | 170 + adev->vm_manager.vram_base_offset; in gfxhub_v3_0_3_init_system_aperture_regs()
303 adev->vm_manager.num_level); in gfxhub_v3_0_3_setup_vmid_config()
320 adev->vm_manager.block_size - 9); in gfxhub_v3_0_3_setup_vmid_config()
333 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
336 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
|
| D | gmc_v6_0.c | 446 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
503 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
527 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
548 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
873 adev->vm_manager.first_kfd_vmid = 8; in gmc_v6_0_sw_init()
881 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
883 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
|
| D | amdgpu_vm.h | 52 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
375 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
376 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
377 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
|
| D | mmhub_v3_0_2.c | 185 adev->vm_manager.vram_base_offset; in mmhub_v3_0_2_init_system_aperture_regs()
322 adev->vm_manager.num_level); in mmhub_v3_0_2_setup_vmid_config()
340 adev->vm_manager.block_size - 9); in mmhub_v3_0_2_setup_vmid_config()
353 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
356 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
|
| D | gfxhub_v3_0.c | 167 + adev->vm_manager.vram_base_offset; in gfxhub_v3_0_init_system_aperture_regs()
300 adev->vm_manager.num_level); in gfxhub_v3_0_setup_vmid_config()
317 adev->vm_manager.block_size - 9); in gfxhub_v3_0_setup_vmid_config()
330 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
333 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
|
| D | mmhub_v3_0_1.c | 192 adev->vm_manager.vram_base_offset; in mmhub_v3_0_1_init_system_aperture_regs()
317 adev->vm_manager.num_level); in mmhub_v3_0_1_setup_vmid_config()
335 adev->vm_manager.block_size - 9); in mmhub_v3_0_1_setup_vmid_config()
348 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
351 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
|
| D | gfxhub_v1_0.c | 255 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
256 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
301 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
304 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
|
| D | mmhub_v3_0.c | 192 adev->vm_manager.vram_base_offset; in mmhub_v3_0_init_system_aperture_regs()
329 adev->vm_manager.num_level); in mmhub_v3_0_setup_vmid_config()
347 adev->vm_manager.block_size - 9); in mmhub_v3_0_setup_vmid_config()
360 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
363 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
|
| D | gfxhub_v2_0.c | 293 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
310 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
323 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
326 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
|
| D | mmhub_v2_0.c | 373 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
391 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
404 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
407 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
|
| D | mmhub_v2_3.c | 291 adev->vm_manager.num_level); in mmhub_v2_3_setup_vmid_config()
309 adev->vm_manager.block_size - 9); in mmhub_v2_3_setup_vmid_config()
322 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
325 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
|
| D | gmc_v7_0.c | 580 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
649 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
678 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
696 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1053 adev->vm_manager.first_kfd_vmid = 8; in gmc_v7_0_sw_init()
1061 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1063 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
|
| D | amdgpu_csa.c | 29 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
|
| D | gmc_v11_0.c | 482 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v11_0_get_vm_pde()
657 adev->vm_manager.vram_base_offset = 0; in gmc_v11_0_vram_gtt_location()
659 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_vram_gtt_location()
821 adev->vm_manager.first_kfd_vmid = 8; in gmc_v11_0_sw_init()
|
| D | mmhub_v1_0.c | 237 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
238 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
279 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
282 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
|
| D | gmc_v8_0.c | 803 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
873 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
917 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
942 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1175 adev->vm_manager.first_kfd_vmid = 8; in gmc_v8_0_sw_init()
1183 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1185 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
|
| D | gfxhub_v2_1.c | 302 adev->vm_manager.num_level); in gfxhub_v2_1_setup_vmid_config()
319 adev->vm_manager.block_size - 9); in gfxhub_v2_1_setup_vmid_config()
332 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
335 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
|
| D | amdgpu_amdkfd.c | 150 ((1 << adev->vm_manager.first_kfd_vmid) - 1), in amdgpu_amdkfd_device_init()
153 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
724 return vmid >= adev->vm_manager.first_kfd_vmid; in amdgpu_amdkfd_is_kfd_vmid()
|
| D | gmc_v9_0.c | 1416 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
1419 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
1610 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1632 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1639 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1712 adev->vm_manager.first_kfd_vmid = in gmc_v9_0_sw_init()
|
| D | si_dma.c | 844 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; in si_dma_set_vm_pte_funcs()
846 adev->vm_manager.vm_pte_scheds[i] = in si_dma_set_vm_pte_funcs()
849 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
|
| /Linux-v6.1/drivers/gpu/drm/radeon/ |
| D | radeon_vm.c | 62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
189 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
196 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
197 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
216 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
[all …]
|
| D | ni.c | 1313 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1315 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1350 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2494 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2499 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2501 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
|
