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Searched refs:uncore (Results 1 – 25 of 140) sorted by relevance

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/Linux-v6.1/drivers/gpu/drm/i915/
Dintel_uncore.c42 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) in fw_domains_get() argument
44 uncore->fw_get_funcs->force_wake_get(uncore, fw_domains); in fw_domains_get()
53 i915->uncore.debug = &i915->mmio_debug; in intel_uncore_mmio_debug_init_early()
56 static void mmio_debug_suspend(struct intel_uncore *uncore) in mmio_debug_suspend() argument
58 if (!uncore->debug) in mmio_debug_suspend()
61 spin_lock(&uncore->debug->lock); in mmio_debug_suspend()
64 if (!uncore->debug->suspend_count++) { in mmio_debug_suspend()
65 uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check; in mmio_debug_suspend()
66 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
69 spin_unlock(&uncore->debug->lock); in mmio_debug_suspend()
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Dvlv_suspend.c111 struct intel_uncore *uncore = &i915->uncore; in vlv_save_gunit_s0ix_state() local
118 s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
119 s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
120 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); in vlv_save_gunit_s0ix_state()
121 s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
122 s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
125 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
127 s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
128 s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
130 s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
[all …]
Dintel_uncore.h90 void (*force_wake_get)(struct intel_uncore *uncore,
95 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
97 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
100 u8 (*mmio_readb)(struct intel_uncore *uncore,
102 u16 (*mmio_readw)(struct intel_uncore *uncore,
104 u32 (*mmio_readl)(struct intel_uncore *uncore,
106 u64 (*mmio_readq)(struct intel_uncore *uncore,
109 void (*mmio_writeb)(struct intel_uncore *uncore,
111 void (*mmio_writew)(struct intel_uncore *uncore,
113 void (*mmio_writel)(struct intel_uncore *uncore,
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Dintel_pcode.c55 static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox, in __snb_pcode_rw() argument
60 lockdep_assert_held(&uncore->i915->sb_lock); in __snb_pcode_rw()
68 if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) in __snb_pcode_rw()
71 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val); in __snb_pcode_rw()
72 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0); in __snb_pcode_rw()
73 intel_uncore_write_fw(uncore, in __snb_pcode_rw()
76 if (__intel_wait_for_register_fw(uncore, in __snb_pcode_rw()
85 *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA); in __snb_pcode_rw()
87 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1); in __snb_pcode_rw()
89 if (GRAPHICS_VER(uncore->i915) > 6) in __snb_pcode_rw()
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Di915_irq.c236 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, in gen3_irq_reset() argument
239 intel_uncore_write(uncore, imr, 0xffffffff); in gen3_irq_reset()
240 intel_uncore_posting_read(uncore, imr); in gen3_irq_reset()
242 intel_uncore_write(uncore, ier, 0); in gen3_irq_reset()
245 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
246 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
247 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
248 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
251 void gen2_irq_reset(struct intel_uncore *uncore) in gen2_irq_reset() argument
253 intel_uncore_write16(uncore, GEN2_IMR, 0xffff); in gen2_irq_reset()
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Dintel_pm.c61 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
62 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | in gen9_init_clock_gating()
67 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
68 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
71 intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, in gen9_init_clock_gating()
72 intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
78 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in gen9_init_clock_gating()
87 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in bxt_init_clock_gating()
94 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in bxt_init_clock_gating()
101 …intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN… in bxt_init_clock_gating()
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Di915_irq.h93 void gen2_irq_reset(struct intel_uncore *uncore);
94 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
97 void gen2_irq_init(struct intel_uncore *uncore,
99 void gen3_irq_init(struct intel_uncore *uncore,
104 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ argument
107 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
111 #define GEN3_IRQ_RESET(uncore, type) \ argument
112 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
114 #define GEN2_IRQ_RESET(uncore) \ argument
115 gen2_irq_reset(uncore)
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Dintel_pcode.h13 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
14 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
16 #define snb_pcode_write(uncore, mbox, val) \ argument
17 snb_pcode_write_timeout(uncore, mbox, val, 500, 0)
19 int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
22 int intel_pcode_init(struct intel_uncore *uncore);
27 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
28 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
Dintel_sbi.c17 struct intel_uncore *uncore = &i915->uncore; in intel_sbi_rw() local
22 if (intel_wait_for_register_fw(uncore, in intel_sbi_rw()
30 intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16); in intel_sbi_rw()
31 intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val); in intel_sbi_rw()
39 intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY); in intel_sbi_rw()
41 if (__intel_wait_for_register_fw(uncore, in intel_sbi_rw()
55 *val = intel_uncore_read_fw(uncore, SBI_DATA); in intel_sbi_rw()
/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_rc6.c48 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
56 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) in set() argument
58 intel_uncore_write_fw(uncore, reg, val); in set()
64 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable() local
75 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); in gen11_rc6_enable()
76 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); in gen11_rc6_enable()
78 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
79 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
81 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen11_rc6_enable()
83 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen11_rc6_enable()
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Dintel_gt_irq.c28 void __iomem * const regs = gt->uncore->regs; in gen11_gt_engine_identity()
138 void __iomem * const regs = gt->uncore->regs; in gen11_gt_bank_handler()
173 void __iomem * const regs = gt->uncore->regs; in gen11_gt_reset_one_iir()
202 struct intel_uncore *uncore = gt->uncore; in gen11_gt_irq_reset() local
205 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); in gen11_gt_irq_reset()
206 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); in gen11_gt_irq_reset()
208 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); in gen11_gt_irq_reset()
210 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); in gen11_gt_irq_reset()
213 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
214 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
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Dintel_gt_clock_utils.c12 static u32 read_reference_ts_freq(struct intel_uncore *uncore) in read_reference_ts_freq() argument
14 u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); in read_reference_ts_freq()
29 static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, in gen11_get_crystal_clock_freq() argument
55 static u32 gen11_read_clock_frequency(struct intel_uncore *uncore) in gen11_read_clock_frequency() argument
57 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen11_read_clock_frequency()
70 freq = read_reference_ts_freq(uncore); in gen11_read_clock_frequency()
72 u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); in gen11_read_clock_frequency()
74 freq = gen11_get_crystal_clock_freq(uncore, c0); in gen11_read_clock_frequency()
88 static u32 gen9_read_clock_frequency(struct intel_uncore *uncore) in gen9_read_clock_frequency() argument
90 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen9_read_clock_frequency()
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Dintel_gt_pm_debugfs.c32 intel_uncore_forcewake_user_get(gt->uncore); in intel_gt_pm_debugfs_forcewake_user_open()
38 intel_uncore_forcewake_user_put(gt->uncore); in intel_gt_pm_debugfs_forcewake_user_release()
70 struct intel_uncore *uncore = gt->uncore; in fw_domains_show() local
75 uncore->user_forcewake_count); in fw_domains_show()
77 for_each_fw_domain(fw_domain, uncore, tmp) in fw_domains_show()
93 with_intel_runtime_pm(gt->uncore->rpm, wakeref) in print_rc6_res()
95 intel_uncore_read(gt->uncore, reg), in print_rc6_res()
102 struct intel_uncore *uncore = gt->uncore; in vlv_drpc() local
105 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); in vlv_drpc()
106 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); in vlv_drpc()
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Dintel_gtt.c418 struct intel_uncore *uncore = gt->uncore; in gtt_write_workarounds() local
427 intel_uncore_write(uncore, in gtt_write_workarounds()
431 intel_uncore_write(uncore, in gtt_write_workarounds()
435 intel_uncore_write(uncore, in gtt_write_workarounds()
439 intel_uncore_write(uncore, in gtt_write_workarounds()
456 intel_uncore_rmw(uncore, in gtt_write_workarounds()
474 intel_uncore_write(uncore, in gtt_write_workarounds()
478 intel_uncore_read(uncore, in gtt_write_workarounds()
483 static void tgl_setup_private_ppat(struct intel_uncore *uncore) in tgl_setup_private_ppat() argument
486 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); in tgl_setup_private_ppat()
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Dintel_sa_media.c16 struct intel_uncore *uncore; in intel_sa_mediagt_setup() local
18 uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL); in intel_sa_mediagt_setup()
19 if (!uncore) in intel_sa_mediagt_setup()
22 uncore->gsi_offset = gsi_offset; in intel_sa_mediagt_setup()
26 intel_uncore_init_early(uncore, gt); in intel_sa_mediagt_setup()
32 uncore->regs = i915->uncore.regs; in intel_sa_mediagt_setup()
33 if (drm_WARN_ON(&i915->drm, uncore->regs == NULL)) in intel_sa_mediagt_setup()
36 gt->uncore = uncore; in intel_sa_mediagt_setup()
Dintel_rps.c43 return rps_to_gt(rps)->uncore; in rps_to_uncore()
65 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) in set() argument
67 intel_uncore_write_fw(uncore, reg, val); in set()
201 intel_uncore_write(gt->uncore, in rps_enable_interrupts()
234 intel_uncore_write(gt->uncore, in rps_disable_interrupts()
272 struct intel_uncore *uncore = rps_to_uncore(rps); in gen5_rps_init() local
292 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); in gen5_rps_init()
310 struct intel_uncore *uncore = in __ips_chipset_val() local
329 total = intel_uncore_read(uncore, DMIEC); in __ips_chipset_val()
330 total += intel_uncore_read(uncore, DDREC); in __ips_chipset_val()
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Dintel_gt.c69 gt->uncore = &i915->uncore; in intel_root_gt_init_early()
131 struct intel_uncore *uncore = gt->uncore; in init_unused_ring() local
133 intel_uncore_write(uncore, RING_CTL(base), 0); in init_unused_ring()
134 intel_uncore_write(uncore, RING_HEAD(base), 0); in init_unused_ring()
135 intel_uncore_write(uncore, RING_TAIL(base), 0); in init_unused_ring()
136 intel_uncore_write(uncore, RING_START(base), 0); in init_unused_ring()
161 struct intel_uncore *uncore = gt->uncore; in intel_gt_init_hw() local
167 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); in intel_gt_init_hw()
170 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf)); in intel_gt_init_hw()
173 intel_uncore_write(uncore, in intel_gt_init_hw()
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Dintel_gt_mcr.c105 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
124 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
150 static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore, in rw_with_mcr_steering_fw() argument
156 lockdep_assert_held(&uncore->lock); in rw_with_mcr_steering_fw()
158 if (GRAPHICS_VER(uncore->i915) >= 11) { in rw_with_mcr_steering_fw()
181 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); in rw_with_mcr_steering_fw()
185 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); in rw_with_mcr_steering_fw()
188 val = intel_uncore_read_fw(uncore, reg); in rw_with_mcr_steering_fw()
190 intel_uncore_write_fw(uncore, reg, value); in rw_with_mcr_steering_fw()
195 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); in rw_with_mcr_steering_fw()
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Dintel_ggtt_fencing.c55 return fence->ggtt->vm.gt->uncore; in fence_to_uncore()
91 struct intel_uncore *uncore = fence_to_uncore(fence); in i965_write_fence_reg() local
103 intel_uncore_write_fw(uncore, fence_reg_lo, 0); in i965_write_fence_reg()
104 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
106 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val)); in i965_write_fence_reg()
107 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val)); in i965_write_fence_reg()
108 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
138 struct intel_uncore *uncore = fence_to_uncore(fence); in i915_write_fence_reg() local
141 intel_uncore_write_fw(uncore, reg, val); in i915_write_fence_reg()
142 intel_uncore_posting_read_fw(uncore, reg); in i915_write_fence_reg()
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Dintel_gt_pm_irq.c16 struct intel_uncore *uncore = gt->uncore; in write_pm_imr() local
29 intel_uncore_write(uncore, reg, mask); in write_pm_imr()
64 struct intel_uncore *uncore = gt->uncore; in gen6_gt_pm_reset_iir() local
69 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
70 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
71 intel_uncore_posting_read(uncore, reg); in gen6_gt_pm_reset_iir()
77 struct intel_uncore *uncore = gt->uncore; in write_pm_ier() local
90 intel_uncore_write(uncore, reg, mask); in write_pm_ier()
/Linux-v6.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fw.c17 static void guc_prepare_xfer(struct intel_uncore *uncore) in guc_prepare_xfer() argument
24 if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50)) in guc_prepare_xfer()
29 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags); in guc_prepare_xfer()
31 if (IS_GEN9_LP(uncore->i915)) in guc_prepare_xfer()
32 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
34 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
36 if (GRAPHICS_VER(uncore->i915) == 9) { in guc_prepare_xfer()
38 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, in guc_prepare_xfer()
42 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF); in guc_prepare_xfer()
47 struct intel_uncore *uncore) in guc_xfer_rsa_mmio() argument
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/Linux-v6.1/drivers/gpu/drm/i915/selftests/
Dintel_uncore.c161 struct intel_uncore *uncore = gt->uncore; in live_forcewake_ops() local
197 wakeref = intel_runtime_pm_get(uncore->rpm); in live_forcewake_ops()
199 for_each_fw_domain(domain, uncore, tmp) { in live_forcewake_ops()
209 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset; in live_forcewake_ops()
216 fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio, in live_forcewake_ops()
221 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
231 intel_uncore_forcewake_get(uncore, fw_domains); in live_forcewake_ops()
233 intel_uncore_forcewake_put(uncore, fw_domains); in live_forcewake_ops()
236 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
268 intel_runtime_pm_put(uncore->rpm, wakeref); in live_forcewake_ops()
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/Linux-v6.1/arch/x86/events/amd/
Duncore.c129 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_add() local
133 if (hwc->idx != -1 && uncore->events[hwc->idx] == event) in amd_uncore_add()
136 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
137 if (uncore->events[i] == event) { in amd_uncore_add()
145 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
146 if (cmpxchg(&uncore->events[i], NULL, event) == NULL) { in amd_uncore_add()
156 hwc->config_base = uncore->msr_base + (2 * hwc->idx); in amd_uncore_add()
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
158 hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx; in amd_uncore_add()
180 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_del() local
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/Linux-v6.1/drivers/gpu/drm/i915/pxp/
Dintel_pxp_session.c23 struct intel_uncore *uncore = pxp_to_gt(pxp)->uncore; in intel_pxp_session_is_in_play() local
28 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) in intel_pxp_session_is_in_play()
29 sip = intel_uncore_read(uncore, GEN12_KCR_SIP); in intel_pxp_session_is_in_play()
36 struct intel_uncore *uncore = pxp_to_gt(pxp)->uncore; in pxp_wait_for_session_state() local
42 wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm); in pxp_wait_for_session_state()
46 ret = intel_wait_for_register(uncore, in pxp_wait_for_session_state()
52 intel_runtime_pm_put(uncore->rpm, wakeref); in pxp_wait_for_session_state()
110 intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1); in pxp_terminate_arb_session_and_global()
161 wakeref = intel_runtime_pm_get_if_in_use(gt->uncore->rpm); in intel_pxp_session_work()
173 intel_runtime_pm_put(gt->uncore->rpm, wakeref); in intel_pxp_session_work()
/Linux-v6.1/arch/x86/events/intel/
Duncore_discovery.c538 struct intel_uncore_type *uncore, in uncore_update_uncore_type() argument
541 uncore->type_id = type->type; in uncore_update_uncore_type()
542 uncore->num_boxes = type->num_boxes; in uncore_update_uncore_type()
543 uncore->num_counters = type->num_counters; in uncore_update_uncore_type()
544 uncore->perf_ctr_bits = type->counter_width; in uncore_update_uncore_type()
545 uncore->box_ids = type->ids; in uncore_update_uncore_type()
549 uncore->ops = &generic_uncore_msr_ops; in uncore_update_uncore_type()
550 uncore->perf_ctr = (unsigned int)type->box_ctrl + type->ctr_offset; in uncore_update_uncore_type()
551 uncore->event_ctl = (unsigned int)type->box_ctrl + type->ctl_offset; in uncore_update_uncore_type()
552 uncore->box_ctl = (unsigned int)type->box_ctrl; in uncore_update_uncore_type()
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