| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | nv20.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
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| D | nv30.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
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| D | nv10.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
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| D | nv35.c | 31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
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| D | nv36.c | 31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
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| D | nv40.c | 31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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| D | nv44.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
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| D | nv25.c | 31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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| D | nv46.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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| D | nv41.c | 30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
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| D | base.c | 35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
168 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
169 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
205 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
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| D | nv47.c | 33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
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| D | nv49.c | 33 .tile.regions = 15,
34 .tile.init = nv30_fb_tile_init,
35 .tile.comp = nv40_fb_tile_comp,
36 .tile.fini = nv20_fb_tile_fini,
37 .tile.prog = nv41_fb_tile_prog,
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| D | nv1a.c | 31 .tile.regions = 8,
32 .tile.init = nv10_fb_tile_init,
33 .tile.fini = nv10_fb_tile_fini,
34 .tile.prog = nv10_fb_tile_prog,
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| D | nv4e.c | 32 .tile.regions = 12,
33 .tile.init = nv46_fb_tile_init,
34 .tile.fini = nv20_fb_tile_fini,
35 .tile.prog = nv44_fb_tile_prog,
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| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv44.c | 31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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| D | nv40.c | 173 nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv40_gr_tile() argument
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
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| D | base.c | 65 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) in nvkm_gr_tile() argument
68 if (gr->func->tile) in nvkm_gr_tile()
69 gr->func->tile(gr, region, tile); in nvkm_gr_tile()
170 .tile = nvkm_gr_tile,
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| D | nv20.c | 149 nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv20_gr_tile() argument
159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile()
160 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile()
161 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile()
164 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile()
166 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile()
168 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr); in nv20_gr_tile()
171 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv20_gr_tile()
173 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); in nv20_gr_tile()
350 .tile = nv20_gr_tile,
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| /Linux-v6.1/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_mman.c | 28 struct tile { struct
42 static u64 tiled_offset(const struct tile *tile, u64 v) in tiled_offset() argument
46 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
49 y = div64_u64_rem(v, tile->stride, &x); in tiled_offset()
50 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; in tiled_offset()
52 if (tile->tiling == I915_TILING_X) { in tiled_offset()
53 v += y * tile->width; in tiled_offset()
54 v += div64_u64_rem(x, tile->width, &x) << tile->size; in tiled_offset()
56 } else if (tile->width == 128) { in tiled_offset()
72 switch (tile->swizzle) { in tiled_offset()
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| /Linux-v6.1/drivers/gpu/ipu-v3/ |
| D | ipu-image-convert.c | 123 struct ipu_image_tile tile[MAX_TILES]; member
678 in_tile = &in->tile[tile_idx]; in fill_tile_column()
679 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; in fill_tile_column()
710 in_tile = &in->tile[tile_idx]; in fill_tile_row()
711 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; in fill_tile_row()
871 struct ipu_image_tile *tile; in calc_tile_dimensions() local
876 tile = &image->tile[ctx->out_tile_map[i]]; in calc_tile_dimensions()
878 tile = &image->tile[i]; in calc_tile_dimensions()
880 tile->size = ((tile->height * image->fmt->bpp) >> 3) * in calc_tile_dimensions()
881 tile->width; in calc_tile_dimensions()
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| /Linux-v6.1/drivers/gpu/drm/nouveau/ |
| D | nouveau_bo.c | 59 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
61 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
65 if (tile->pitch) in nv10_bo_update_tile_region()
66 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
71 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region() local
80 spin_lock(&drm->tile.lock); in nv10_bo_get_tile_region()
82 if (!tile->used && in nv10_bo_get_tile_region()
83 (!tile->fence || nouveau_fence_done(tile->fence))) in nv10_bo_get_tile_region()
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| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v7_0.c | 1030 uint32_t *tile, *macrotile; in gfx_v7_0_tiling_mode_table_init() local
1032 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1049 tile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1055 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1059 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1063 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1067 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1071 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1075 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1078 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
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| /Linux-v6.1/drivers/hid/ |
| D | hid-picolcd_fb.c | 91 int chip, int tile) in picolcd_fb_send_tile() argument
114 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
127 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
142 int chip, int tile) in picolcd_fb_update_tile() argument
146 u8 *vdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_update_tile()
150 const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32; in picolcd_fb_update_tile()
158 const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8; in picolcd_fb_update_tile()
227 int chip, tile, n; in picolcd_fb_update() local
248 for (tile = 0; tile < 8; tile++) { in picolcd_fb_update()
251 fbdata->bpp, chip, tile)) in picolcd_fb_update()
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| /Linux-v6.1/arch/arm/mach-versatile/ |
| D | Kconfig | 129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
178 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
180 core tile options should be enabled.
187 Enable support for the ARM1136 tile fitted to the
194 Enable support for the ARM1176 tile fitted to the
201 Enable support for the Cortex-A9MPCore tile fitted to the
209 Enable support for the ARM11MPCore tile fitted to the Realview(R)
296 tile support or Flattened Device Tree based support options.
311 The TC2 (A15x2 A7x3) versatile express core tile integrates a logic
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