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Searched refs:rtl8188e_PHY_SetBBReg (Results 1 – 9 of 9) sorted by relevance

/Linux-v6.1/drivers/staging/r8188eu/hal/
Dodm_RTL8188E.c13 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25)));… in odm_RX_HWAntDivInit()
15 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870… in odm_RX_HWAntDivInit()
16 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by… in odm_RX_HWAntDivInit()
17 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/… in odm_RX_HWAntDivInit()
18 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at C… in odm_RX_HWAntDivInit()
20 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); in odm_RX_HWAntDivInit()
22 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report i… in odm_RX_HWAntDivInit()
23 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv… in odm_RX_HWAntDivInit()
25 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table… in odm_RX_HWAntDivInit()
35 …rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25)));… in odm_TRX_HWAntDivInit()
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DHalPhyRf_8188e.c285 rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); in phy_PathA_IQK_8188E()
286 rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); in phy_PathA_IQK_8188E()
287 rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); in phy_PathA_IQK_8188E()
288 rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); in phy_PathA_IQK_8188E()
291 rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); in phy_PathA_IQK_8188E()
294 rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); in phy_PathA_IQK_8188E()
295 rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); in phy_PathA_IQK_8188E()
321 rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); in phy_PathA_RxIQK()
331 rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); in phy_PathA_RxIQK()
334 rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00); in phy_PathA_RxIQK()
[all …]
Drtl8188e_phycfg.c74 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) in rtl8188e_PHY_SetBBReg() function
142 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge)); in phy_RFSerialRead()
145 rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); in phy_RFSerialRead()
232 rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in phy_RFSerialWrite()
505 rtl8188e_PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); in PHY_BBConfig8188E()
626 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in _PHY_SetBWMode92C()
627 rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); in _PHY_SetBWMode92C()
631 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in _PHY_SetBWMode92C()
632 rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); in _PHY_SetBWMode92C()
634 rtl8188e_PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); in _PHY_SetBWMode92C()
[all …]
Dodm.c332 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ in odm_FalseAlarmCounterStatistics()
333 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ in odm_FalseAlarmCounterStatistics()
356 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); in odm_FalseAlarmCounterStatistics()
357 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); in odm_FalseAlarmCounterStatistics()
648 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI); in ODM_Write_DIG()
699 rtl8188e_PHY_SetBBReg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ in ODM_RF_Saving()
700 rtl8188e_PHY_SetBBReg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */ in ODM_RF_Saving()
701 rtl8188e_PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ in ODM_RF_Saving()
702 rtl8188e_PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ in ODM_RF_Saving()
703 rtl8188e_PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ in ODM_RF_Saving()
[all …]
Drtl8188e_rf6052.c141 rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
143 rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
147 rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
149 rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
291 rtl8188e_PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal); in writeOFDMPowerReg88E()
384 rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); in phy_RF6052_Config_ParaFile()
388 rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); in phy_RF6052_Config_ParaFile()
392 …rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bit… in phy_RF6052_Config_ParaFile()
395 …rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits… in phy_RF6052_Config_ParaFile()
403 rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); in phy_RF6052_Config_ParaFile()
DHalHWImg8188E_BB.c171 rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data); in odm_ConfigBB_AGC_8188E()
468 rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data); in odm_ConfigBB_PHY_8188E()
Dusb_halinit.c509 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock()
510 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
527 rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01); in _InitAntenna_Selection()
/Linux-v6.1/drivers/staging/r8188eu/include/
DHal8188EPhyCfg.h74 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
/Linux-v6.1/drivers/staging/r8188eu/os_dep/
Dioctl_linux.c3274 rtl8188e_PHY_SetBBReg(padapter, arg, 0xffffffff, extra_arg); in rtw_dbg_port()