1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 *
5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/power_supply.h>
26 #include <linux/regmap.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/usb/of.h>
29 #include <linux/usb/otg.h>
30
31 #define BIT_WRITEABLE_SHIFT 16
32 #define SCHEDULE_DELAY (60 * HZ)
33 #define OTG_SCHEDULE_DELAY (2 * HZ)
34
35 enum rockchip_usb2phy_port_id {
36 USB2PHY_PORT_OTG,
37 USB2PHY_PORT_HOST,
38 USB2PHY_NUM_PORTS,
39 };
40
41 enum rockchip_usb2phy_host_state {
42 PHY_STATE_HS_ONLINE = 0,
43 PHY_STATE_DISCONNECT = 1,
44 PHY_STATE_CONNECT = 2,
45 PHY_STATE_FS_LS_ONLINE = 4,
46 };
47
48 /**
49 * enum usb_chg_state - Different states involved in USB charger detection.
50 * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection
51 * process is not yet started.
52 * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact.
53 * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected.
54 * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects
55 * between SDP and DCP/CDP).
56 * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
57 * between DCP and CDP).
58 * @USB_CHG_STATE_DETECTED: USB charger type is determined.
59 */
60 enum usb_chg_state {
61 USB_CHG_STATE_UNDEFINED = 0,
62 USB_CHG_STATE_WAIT_FOR_DCD,
63 USB_CHG_STATE_DCD_DONE,
64 USB_CHG_STATE_PRIMARY_DONE,
65 USB_CHG_STATE_SECONDARY_DONE,
66 USB_CHG_STATE_DETECTED,
67 };
68
69 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
70 EXTCON_USB,
71 EXTCON_USB_HOST,
72 EXTCON_CHG_USB_SDP,
73 EXTCON_CHG_USB_CDP,
74 EXTCON_CHG_USB_DCP,
75 EXTCON_CHG_USB_SLOW,
76 EXTCON_NONE,
77 };
78
79 struct usb2phy_reg {
80 unsigned int offset;
81 unsigned int bitend;
82 unsigned int bitstart;
83 unsigned int disable;
84 unsigned int enable;
85 };
86
87 /**
88 * struct rockchip_chg_det_reg - usb charger detect registers
89 * @cp_det: charging port detected successfully.
90 * @dcp_det: dedicated charging port detected successfully.
91 * @dp_det: assert data pin connect successfully.
92 * @idm_sink_en: open dm sink curren.
93 * @idp_sink_en: open dp sink current.
94 * @idp_src_en: open dm source current.
95 * @rdm_pdwn_en: open dm pull down resistor.
96 * @vdm_src_en: open dm voltage source.
97 * @vdp_src_en: open dp voltage source.
98 * @opmode: utmi operational mode.
99 */
100 struct rockchip_chg_det_reg {
101 struct usb2phy_reg cp_det;
102 struct usb2phy_reg dcp_det;
103 struct usb2phy_reg dp_det;
104 struct usb2phy_reg idm_sink_en;
105 struct usb2phy_reg idp_sink_en;
106 struct usb2phy_reg idp_src_en;
107 struct usb2phy_reg rdm_pdwn_en;
108 struct usb2phy_reg vdm_src_en;
109 struct usb2phy_reg vdp_src_en;
110 struct usb2phy_reg opmode;
111 };
112
113 /**
114 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
115 * @phy_sus: phy suspend register.
116 * @bvalid_det_en: vbus valid rise detection enable register.
117 * @bvalid_det_st: vbus valid rise detection status register.
118 * @bvalid_det_clr: vbus valid rise detection clear register.
119 * @id_det_en: id detection enable register.
120 * @id_det_st: id detection state register.
121 * @id_det_clr: id detection clear register.
122 * @ls_det_en: linestate detection enable register.
123 * @ls_det_st: linestate detection state register.
124 * @ls_det_clr: linestate detection clear register.
125 * @utmi_avalid: utmi vbus avalid status register.
126 * @utmi_bvalid: utmi vbus bvalid status register.
127 * @utmi_id: utmi id state register.
128 * @utmi_ls: utmi linestate state register.
129 * @utmi_hstdet: utmi host disconnect register.
130 */
131 struct rockchip_usb2phy_port_cfg {
132 struct usb2phy_reg phy_sus;
133 struct usb2phy_reg bvalid_det_en;
134 struct usb2phy_reg bvalid_det_st;
135 struct usb2phy_reg bvalid_det_clr;
136 struct usb2phy_reg id_det_en;
137 struct usb2phy_reg id_det_st;
138 struct usb2phy_reg id_det_clr;
139 struct usb2phy_reg ls_det_en;
140 struct usb2phy_reg ls_det_st;
141 struct usb2phy_reg ls_det_clr;
142 struct usb2phy_reg utmi_avalid;
143 struct usb2phy_reg utmi_bvalid;
144 struct usb2phy_reg utmi_id;
145 struct usb2phy_reg utmi_ls;
146 struct usb2phy_reg utmi_hstdet;
147 };
148
149 /**
150 * struct rockchip_usb2phy_cfg - usb-phy configuration.
151 * @reg: the address offset of grf for usb-phy config.
152 * @num_ports: specify how many ports that the phy has.
153 * @clkout_ctl: keep on/turn off output clk of phy.
154 * @port_cfgs: usb-phy port configurations.
155 * @chg_det: charger detection registers.
156 */
157 struct rockchip_usb2phy_cfg {
158 unsigned int reg;
159 unsigned int num_ports;
160 struct usb2phy_reg clkout_ctl;
161 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
162 const struct rockchip_chg_det_reg chg_det;
163 };
164
165 /**
166 * struct rockchip_usb2phy_port - usb-phy port data.
167 * @phy: generic phy.
168 * @port_id: flag for otg port or host port.
169 * @suspended: phy suspended flag.
170 * @vbus_attached: otg device vbus status.
171 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
172 * @id_irq: IRQ number assigned for ID pin detection.
173 * @ls_irq: IRQ number assigned for linestate detection.
174 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
175 * irqs to one irq in otg-port.
176 * @mutex: for register updating in sm_work.
177 * @chg_work: charge detect work.
178 * @otg_sm_work: OTG state machine work.
179 * @sm_work: HOST state machine work.
180 * @port_cfg: port register configuration, assigned by driver data.
181 * @event_nb: hold event notification callback.
182 * @state: define OTG enumeration states before device reset.
183 * @mode: the dr_mode of the controller.
184 */
185 struct rockchip_usb2phy_port {
186 struct phy *phy;
187 unsigned int port_id;
188 bool suspended;
189 bool vbus_attached;
190 int bvalid_irq;
191 int id_irq;
192 int ls_irq;
193 int otg_mux_irq;
194 struct mutex mutex;
195 struct delayed_work chg_work;
196 struct delayed_work otg_sm_work;
197 struct delayed_work sm_work;
198 const struct rockchip_usb2phy_port_cfg *port_cfg;
199 struct notifier_block event_nb;
200 enum usb_otg_state state;
201 enum usb_dr_mode mode;
202 };
203
204 /**
205 * struct rockchip_usb2phy - usb2.0 phy driver data.
206 * @dev: pointer to device.
207 * @grf: General Register Files regmap.
208 * @usbgrf: USB General Register Files regmap.
209 * @clk: clock struct of phy input clk.
210 * @clk480m: clock struct of phy output clk.
211 * @clk480m_hw: clock struct of phy output clk management.
212 * @chg_state: states involved in USB charger detection.
213 * @chg_type: USB charger types.
214 * @dcd_retries: The retry count used to track Data contact
215 * detection process.
216 * @edev: extcon device for notification registration
217 * @irq: muxed interrupt for single irq configuration
218 * @phy_cfg: phy register configuration, assigned by driver data.
219 * @ports: phy port instance.
220 */
221 struct rockchip_usb2phy {
222 struct device *dev;
223 struct regmap *grf;
224 struct regmap *usbgrf;
225 struct clk *clk;
226 struct clk *clk480m;
227 struct clk_hw clk480m_hw;
228 enum usb_chg_state chg_state;
229 enum power_supply_type chg_type;
230 u8 dcd_retries;
231 struct extcon_dev *edev;
232 int irq;
233 const struct rockchip_usb2phy_cfg *phy_cfg;
234 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
235 };
236
get_reg_base(struct rockchip_usb2phy * rphy)237 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
238 {
239 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
240 }
241
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)242 static inline int property_enable(struct regmap *base,
243 const struct usb2phy_reg *reg, bool en)
244 {
245 unsigned int val, mask, tmp;
246
247 tmp = en ? reg->enable : reg->disable;
248 mask = GENMASK(reg->bitend, reg->bitstart);
249 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
250
251 return regmap_write(base, reg->offset, val);
252 }
253
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)254 static inline bool property_enabled(struct regmap *base,
255 const struct usb2phy_reg *reg)
256 {
257 int ret;
258 unsigned int tmp, orig;
259 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
260
261 ret = regmap_read(base, reg->offset, &orig);
262 if (ret)
263 return false;
264
265 tmp = (orig & mask) >> reg->bitstart;
266 return tmp != reg->disable;
267 }
268
rockchip_usb2phy_clk480m_prepare(struct clk_hw * hw)269 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
270 {
271 struct rockchip_usb2phy *rphy =
272 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
273 struct regmap *base = get_reg_base(rphy);
274 int ret;
275
276 /* turn on 480m clk output if it is off */
277 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
278 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
279 if (ret)
280 return ret;
281
282 /* waiting for the clk become stable */
283 usleep_range(1200, 1300);
284 }
285
286 return 0;
287 }
288
rockchip_usb2phy_clk480m_unprepare(struct clk_hw * hw)289 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
290 {
291 struct rockchip_usb2phy *rphy =
292 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
293 struct regmap *base = get_reg_base(rphy);
294
295 /* turn off 480m clk output */
296 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
297 }
298
rockchip_usb2phy_clk480m_prepared(struct clk_hw * hw)299 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
300 {
301 struct rockchip_usb2phy *rphy =
302 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
303 struct regmap *base = get_reg_base(rphy);
304
305 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
306 }
307
308 static unsigned long
rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)309 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
310 unsigned long parent_rate)
311 {
312 return 480000000;
313 }
314
315 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
316 .prepare = rockchip_usb2phy_clk480m_prepare,
317 .unprepare = rockchip_usb2phy_clk480m_unprepare,
318 .is_prepared = rockchip_usb2phy_clk480m_prepared,
319 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
320 };
321
rockchip_usb2phy_clk480m_unregister(void * data)322 static void rockchip_usb2phy_clk480m_unregister(void *data)
323 {
324 struct rockchip_usb2phy *rphy = data;
325
326 of_clk_del_provider(rphy->dev->of_node);
327 clk_unregister(rphy->clk480m);
328 }
329
330 static int
rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy * rphy)331 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
332 {
333 struct device_node *node = rphy->dev->of_node;
334 struct clk_init_data init;
335 const char *clk_name;
336 int ret = 0;
337
338 init.flags = 0;
339 init.name = "clk_usbphy_480m";
340 init.ops = &rockchip_usb2phy_clkout_ops;
341
342 /* optional override of the clockname */
343 of_property_read_string(node, "clock-output-names", &init.name);
344
345 if (rphy->clk) {
346 clk_name = __clk_get_name(rphy->clk);
347 init.parent_names = &clk_name;
348 init.num_parents = 1;
349 } else {
350 init.parent_names = NULL;
351 init.num_parents = 0;
352 }
353
354 rphy->clk480m_hw.init = &init;
355
356 /* register the clock */
357 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
358 if (IS_ERR(rphy->clk480m)) {
359 ret = PTR_ERR(rphy->clk480m);
360 goto err_ret;
361 }
362
363 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
364 if (ret < 0)
365 goto err_clk_provider;
366
367 return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy);
368
369 err_clk_provider:
370 clk_unregister(rphy->clk480m);
371 err_ret:
372 return ret;
373 }
374
rockchip_usb2phy_extcon_register(struct rockchip_usb2phy * rphy)375 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
376 {
377 int ret;
378 struct device_node *node = rphy->dev->of_node;
379 struct extcon_dev *edev;
380
381 if (of_property_read_bool(node, "extcon")) {
382 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
383 if (IS_ERR(edev)) {
384 if (PTR_ERR(edev) != -EPROBE_DEFER)
385 dev_err(rphy->dev, "Invalid or missing extcon\n");
386 return PTR_ERR(edev);
387 }
388 } else {
389 /* Initialize extcon device */
390 edev = devm_extcon_dev_allocate(rphy->dev,
391 rockchip_usb2phy_extcon_cable);
392
393 if (IS_ERR(edev))
394 return -ENOMEM;
395
396 ret = devm_extcon_dev_register(rphy->dev, edev);
397 if (ret) {
398 dev_err(rphy->dev, "failed to register extcon device\n");
399 return ret;
400 }
401 }
402
403 rphy->edev = edev;
404
405 return 0;
406 }
407
rockchip_usb2phy_init(struct phy * phy)408 static int rockchip_usb2phy_init(struct phy *phy)
409 {
410 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
411 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
412 int ret = 0;
413
414 mutex_lock(&rport->mutex);
415
416 if (rport->port_id == USB2PHY_PORT_OTG) {
417 if (rport->mode != USB_DR_MODE_HOST &&
418 rport->mode != USB_DR_MODE_UNKNOWN) {
419 /* clear bvalid status and enable bvalid detect irq */
420 ret = property_enable(rphy->grf,
421 &rport->port_cfg->bvalid_det_clr,
422 true);
423 if (ret)
424 goto out;
425
426 ret = property_enable(rphy->grf,
427 &rport->port_cfg->bvalid_det_en,
428 true);
429 if (ret)
430 goto out;
431
432 /* clear id status and enable id detect irq */
433 ret = property_enable(rphy->grf,
434 &rport->port_cfg->id_det_clr,
435 true);
436 if (ret)
437 goto out;
438
439 ret = property_enable(rphy->grf,
440 &rport->port_cfg->id_det_en,
441 true);
442 if (ret)
443 goto out;
444
445 schedule_delayed_work(&rport->otg_sm_work,
446 OTG_SCHEDULE_DELAY * 3);
447 } else {
448 /* If OTG works in host only mode, do nothing. */
449 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
450 }
451 } else if (rport->port_id == USB2PHY_PORT_HOST) {
452 /* clear linestate and enable linestate detect irq */
453 ret = property_enable(rphy->grf,
454 &rport->port_cfg->ls_det_clr, true);
455 if (ret)
456 goto out;
457
458 ret = property_enable(rphy->grf,
459 &rport->port_cfg->ls_det_en, true);
460 if (ret)
461 goto out;
462
463 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
464 }
465
466 out:
467 mutex_unlock(&rport->mutex);
468 return ret;
469 }
470
rockchip_usb2phy_power_on(struct phy * phy)471 static int rockchip_usb2phy_power_on(struct phy *phy)
472 {
473 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
474 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
475 struct regmap *base = get_reg_base(rphy);
476 int ret;
477
478 dev_dbg(&rport->phy->dev, "port power on\n");
479
480 if (!rport->suspended)
481 return 0;
482
483 ret = clk_prepare_enable(rphy->clk480m);
484 if (ret)
485 return ret;
486
487 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
488 if (ret)
489 return ret;
490
491 /* waiting for the utmi_clk to become stable */
492 usleep_range(1500, 2000);
493
494 rport->suspended = false;
495 return 0;
496 }
497
rockchip_usb2phy_power_off(struct phy * phy)498 static int rockchip_usb2phy_power_off(struct phy *phy)
499 {
500 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
501 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
502 struct regmap *base = get_reg_base(rphy);
503 int ret;
504
505 dev_dbg(&rport->phy->dev, "port power off\n");
506
507 if (rport->suspended)
508 return 0;
509
510 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
511 if (ret)
512 return ret;
513
514 rport->suspended = true;
515 clk_disable_unprepare(rphy->clk480m);
516
517 return 0;
518 }
519
rockchip_usb2phy_exit(struct phy * phy)520 static int rockchip_usb2phy_exit(struct phy *phy)
521 {
522 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
523
524 if (rport->port_id == USB2PHY_PORT_OTG &&
525 rport->mode != USB_DR_MODE_HOST &&
526 rport->mode != USB_DR_MODE_UNKNOWN) {
527 cancel_delayed_work_sync(&rport->otg_sm_work);
528 cancel_delayed_work_sync(&rport->chg_work);
529 } else if (rport->port_id == USB2PHY_PORT_HOST)
530 cancel_delayed_work_sync(&rport->sm_work);
531
532 return 0;
533 }
534
535 static const struct phy_ops rockchip_usb2phy_ops = {
536 .init = rockchip_usb2phy_init,
537 .exit = rockchip_usb2phy_exit,
538 .power_on = rockchip_usb2phy_power_on,
539 .power_off = rockchip_usb2phy_power_off,
540 .owner = THIS_MODULE,
541 };
542
rockchip_usb2phy_otg_sm_work(struct work_struct * work)543 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
544 {
545 struct rockchip_usb2phy_port *rport =
546 container_of(work, struct rockchip_usb2phy_port,
547 otg_sm_work.work);
548 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
549 static unsigned int cable;
550 unsigned long delay;
551 bool vbus_attach, sch_work, notify_charger;
552
553 vbus_attach = property_enabled(rphy->grf,
554 &rport->port_cfg->utmi_bvalid);
555
556 sch_work = false;
557 notify_charger = false;
558 delay = OTG_SCHEDULE_DELAY;
559 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
560 usb_otg_state_string(rport->state));
561
562 switch (rport->state) {
563 case OTG_STATE_UNDEFINED:
564 rport->state = OTG_STATE_B_IDLE;
565 if (!vbus_attach)
566 rockchip_usb2phy_power_off(rport->phy);
567 fallthrough;
568 case OTG_STATE_B_IDLE:
569 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
570 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
571 rport->state = OTG_STATE_A_HOST;
572 rockchip_usb2phy_power_on(rport->phy);
573 return;
574 } else if (vbus_attach) {
575 dev_dbg(&rport->phy->dev, "vbus_attach\n");
576 switch (rphy->chg_state) {
577 case USB_CHG_STATE_UNDEFINED:
578 schedule_delayed_work(&rport->chg_work, 0);
579 return;
580 case USB_CHG_STATE_DETECTED:
581 switch (rphy->chg_type) {
582 case POWER_SUPPLY_TYPE_USB:
583 dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
584 rockchip_usb2phy_power_on(rport->phy);
585 rport->state = OTG_STATE_B_PERIPHERAL;
586 notify_charger = true;
587 sch_work = true;
588 cable = EXTCON_CHG_USB_SDP;
589 break;
590 case POWER_SUPPLY_TYPE_USB_DCP:
591 dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
592 rockchip_usb2phy_power_off(rport->phy);
593 notify_charger = true;
594 sch_work = true;
595 cable = EXTCON_CHG_USB_DCP;
596 break;
597 case POWER_SUPPLY_TYPE_USB_CDP:
598 dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
599 rockchip_usb2phy_power_on(rport->phy);
600 rport->state = OTG_STATE_B_PERIPHERAL;
601 notify_charger = true;
602 sch_work = true;
603 cable = EXTCON_CHG_USB_CDP;
604 break;
605 default:
606 break;
607 }
608 break;
609 default:
610 break;
611 }
612 } else {
613 notify_charger = true;
614 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
615 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
616 }
617
618 if (rport->vbus_attached != vbus_attach) {
619 rport->vbus_attached = vbus_attach;
620
621 if (notify_charger && rphy->edev) {
622 extcon_set_state_sync(rphy->edev,
623 cable, vbus_attach);
624 if (cable == EXTCON_CHG_USB_SDP)
625 extcon_set_state_sync(rphy->edev,
626 EXTCON_USB,
627 vbus_attach);
628 }
629 }
630 break;
631 case OTG_STATE_B_PERIPHERAL:
632 if (!vbus_attach) {
633 dev_dbg(&rport->phy->dev, "usb disconnect\n");
634 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
635 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
636 rport->state = OTG_STATE_B_IDLE;
637 delay = 0;
638 rockchip_usb2phy_power_off(rport->phy);
639 }
640 sch_work = true;
641 break;
642 case OTG_STATE_A_HOST:
643 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
644 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
645 rport->state = OTG_STATE_B_IDLE;
646 rockchip_usb2phy_power_off(rport->phy);
647 }
648 break;
649 default:
650 break;
651 }
652
653 if (sch_work)
654 schedule_delayed_work(&rport->otg_sm_work, delay);
655 }
656
chg_to_string(enum power_supply_type chg_type)657 static const char *chg_to_string(enum power_supply_type chg_type)
658 {
659 switch (chg_type) {
660 case POWER_SUPPLY_TYPE_USB:
661 return "USB_SDP_CHARGER";
662 case POWER_SUPPLY_TYPE_USB_DCP:
663 return "USB_DCP_CHARGER";
664 case POWER_SUPPLY_TYPE_USB_CDP:
665 return "USB_CDP_CHARGER";
666 default:
667 return "INVALID_CHARGER";
668 }
669 }
670
rockchip_chg_enable_dcd(struct rockchip_usb2phy * rphy,bool en)671 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
672 bool en)
673 {
674 struct regmap *base = get_reg_base(rphy);
675
676 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
677 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
678 }
679
rockchip_chg_enable_primary_det(struct rockchip_usb2phy * rphy,bool en)680 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
681 bool en)
682 {
683 struct regmap *base = get_reg_base(rphy);
684
685 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
686 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
687 }
688
rockchip_chg_enable_secondary_det(struct rockchip_usb2phy * rphy,bool en)689 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
690 bool en)
691 {
692 struct regmap *base = get_reg_base(rphy);
693
694 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
695 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
696 }
697
698 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
699 #define CHG_DCD_MAX_RETRIES 6
700 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
701 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
rockchip_chg_detect_work(struct work_struct * work)702 static void rockchip_chg_detect_work(struct work_struct *work)
703 {
704 struct rockchip_usb2phy_port *rport =
705 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
706 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
707 struct regmap *base = get_reg_base(rphy);
708 bool is_dcd, tmout, vout;
709 unsigned long delay;
710
711 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
712 rphy->chg_state);
713 switch (rphy->chg_state) {
714 case USB_CHG_STATE_UNDEFINED:
715 if (!rport->suspended)
716 rockchip_usb2phy_power_off(rport->phy);
717 /* put the controller in non-driving mode */
718 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
719 /* Start DCD processing stage 1 */
720 rockchip_chg_enable_dcd(rphy, true);
721 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
722 rphy->dcd_retries = 0;
723 delay = CHG_DCD_POLL_TIME;
724 break;
725 case USB_CHG_STATE_WAIT_FOR_DCD:
726 /* get data contact detection status */
727 is_dcd = property_enabled(rphy->grf,
728 &rphy->phy_cfg->chg_det.dp_det);
729 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
730 /* stage 2 */
731 if (is_dcd || tmout) {
732 /* stage 4 */
733 /* Turn off DCD circuitry */
734 rockchip_chg_enable_dcd(rphy, false);
735 /* Voltage Source on DP, Probe on DM */
736 rockchip_chg_enable_primary_det(rphy, true);
737 delay = CHG_PRIMARY_DET_TIME;
738 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
739 } else {
740 /* stage 3 */
741 delay = CHG_DCD_POLL_TIME;
742 }
743 break;
744 case USB_CHG_STATE_DCD_DONE:
745 vout = property_enabled(rphy->grf,
746 &rphy->phy_cfg->chg_det.cp_det);
747 rockchip_chg_enable_primary_det(rphy, false);
748 if (vout) {
749 /* Voltage Source on DM, Probe on DP */
750 rockchip_chg_enable_secondary_det(rphy, true);
751 delay = CHG_SECONDARY_DET_TIME;
752 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
753 } else {
754 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
755 /* floating charger found */
756 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
757 rphy->chg_state = USB_CHG_STATE_DETECTED;
758 delay = 0;
759 } else {
760 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
761 rphy->chg_state = USB_CHG_STATE_DETECTED;
762 delay = 0;
763 }
764 }
765 break;
766 case USB_CHG_STATE_PRIMARY_DONE:
767 vout = property_enabled(rphy->grf,
768 &rphy->phy_cfg->chg_det.dcp_det);
769 /* Turn off voltage source */
770 rockchip_chg_enable_secondary_det(rphy, false);
771 if (vout)
772 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
773 else
774 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
775 fallthrough;
776 case USB_CHG_STATE_SECONDARY_DONE:
777 rphy->chg_state = USB_CHG_STATE_DETECTED;
778 fallthrough;
779 case USB_CHG_STATE_DETECTED:
780 /* put the controller in normal mode */
781 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
782 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
783 dev_dbg(&rport->phy->dev, "charger = %s\n",
784 chg_to_string(rphy->chg_type));
785 return;
786 default:
787 return;
788 }
789
790 schedule_delayed_work(&rport->chg_work, delay);
791 }
792
793 /*
794 * The function manage host-phy port state and suspend/resume phy port
795 * to save power.
796 *
797 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
798 * devices is disconnect or not. Besides, we do not need care it is FS/LS
799 * disconnected or HS disconnected, actually, we just only need get the
800 * device is disconnected at last through rearm the delayed work,
801 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
802 *
803 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
804 * some clk related APIs, so do not invoke it from interrupt context directly.
805 */
rockchip_usb2phy_sm_work(struct work_struct * work)806 static void rockchip_usb2phy_sm_work(struct work_struct *work)
807 {
808 struct rockchip_usb2phy_port *rport =
809 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
810 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
811 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
812 rport->port_cfg->utmi_hstdet.bitstart + 1;
813 unsigned int ul, uhd, state;
814 unsigned int ul_mask, uhd_mask;
815 int ret;
816
817 mutex_lock(&rport->mutex);
818
819 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
820 if (ret < 0)
821 goto next_schedule;
822
823 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
824 if (ret < 0)
825 goto next_schedule;
826
827 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
828 rport->port_cfg->utmi_hstdet.bitstart);
829 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
830 rport->port_cfg->utmi_ls.bitstart);
831
832 /* stitch on utmi_ls and utmi_hstdet as phy state */
833 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
834 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
835
836 switch (state) {
837 case PHY_STATE_HS_ONLINE:
838 dev_dbg(&rport->phy->dev, "HS online\n");
839 break;
840 case PHY_STATE_FS_LS_ONLINE:
841 /*
842 * For FS/LS device, the online state share with connect state
843 * from utmi_ls and utmi_hstdet register, so we distinguish
844 * them via suspended flag.
845 *
846 * Plus, there are two cases, one is D- Line pull-up, and D+
847 * line pull-down, the state is 4; another is D+ line pull-up,
848 * and D- line pull-down, the state is 2.
849 */
850 if (!rport->suspended) {
851 /* D- line pull-up, D+ line pull-down */
852 dev_dbg(&rport->phy->dev, "FS/LS online\n");
853 break;
854 }
855 fallthrough;
856 case PHY_STATE_CONNECT:
857 if (rport->suspended) {
858 dev_dbg(&rport->phy->dev, "Connected\n");
859 rockchip_usb2phy_power_on(rport->phy);
860 rport->suspended = false;
861 } else {
862 /* D+ line pull-up, D- line pull-down */
863 dev_dbg(&rport->phy->dev, "FS/LS online\n");
864 }
865 break;
866 case PHY_STATE_DISCONNECT:
867 if (!rport->suspended) {
868 dev_dbg(&rport->phy->dev, "Disconnected\n");
869 rockchip_usb2phy_power_off(rport->phy);
870 rport->suspended = true;
871 }
872
873 /*
874 * activate the linestate detection to get the next device
875 * plug-in irq.
876 */
877 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
878 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
879
880 /*
881 * we don't need to rearm the delayed work when the phy port
882 * is suspended.
883 */
884 mutex_unlock(&rport->mutex);
885 return;
886 default:
887 dev_dbg(&rport->phy->dev, "unknown phy state\n");
888 break;
889 }
890
891 next_schedule:
892 mutex_unlock(&rport->mutex);
893 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
894 }
895
rockchip_usb2phy_linestate_irq(int irq,void * data)896 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
897 {
898 struct rockchip_usb2phy_port *rport = data;
899 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
900
901 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
902 return IRQ_NONE;
903
904 mutex_lock(&rport->mutex);
905
906 /* disable linestate detect irq and clear its status */
907 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
908 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
909
910 mutex_unlock(&rport->mutex);
911
912 /*
913 * In this case for host phy port, a new device is plugged in,
914 * meanwhile, if the phy port is suspended, we need rearm the work to
915 * resume it and mange its states; otherwise, we do nothing about that.
916 */
917 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
918 rockchip_usb2phy_sm_work(&rport->sm_work.work);
919
920 return IRQ_HANDLED;
921 }
922
rockchip_usb2phy_bvalid_irq(int irq,void * data)923 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
924 {
925 struct rockchip_usb2phy_port *rport = data;
926 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
927
928 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
929 return IRQ_NONE;
930
931 /* clear bvalid detect irq pending status */
932 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
933
934 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
935
936 return IRQ_HANDLED;
937 }
938
rockchip_usb2phy_id_irq(int irq,void * data)939 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
940 {
941 struct rockchip_usb2phy_port *rport = data;
942 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
943 bool id;
944
945 if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st))
946 return IRQ_NONE;
947
948 /* clear id detect irq pending status */
949 property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true);
950
951 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
952 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
953
954 return IRQ_HANDLED;
955 }
956
rockchip_usb2phy_otg_mux_irq(int irq,void * data)957 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
958 {
959 irqreturn_t ret = IRQ_NONE;
960
961 ret |= rockchip_usb2phy_bvalid_irq(irq, data);
962 ret |= rockchip_usb2phy_id_irq(irq, data);
963
964 return ret;
965 }
966
rockchip_usb2phy_irq(int irq,void * data)967 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
968 {
969 struct rockchip_usb2phy *rphy = data;
970 struct rockchip_usb2phy_port *rport;
971 irqreturn_t ret = IRQ_NONE;
972 unsigned int index;
973
974 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
975 rport = &rphy->ports[index];
976 if (!rport->phy)
977 continue;
978
979 switch (rport->port_id) {
980 case USB2PHY_PORT_OTG:
981 if (rport->mode != USB_DR_MODE_HOST &&
982 rport->mode != USB_DR_MODE_UNKNOWN)
983 ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
984 break;
985 case USB2PHY_PORT_HOST:
986 ret |= rockchip_usb2phy_linestate_irq(irq, rport);
987 break;
988 }
989 }
990
991 return ret;
992 }
993
rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)994 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
995 struct rockchip_usb2phy_port *rport,
996 struct device_node *child_np)
997 {
998 int ret;
999
1000 /*
1001 * If the usb2 phy used combined irq for otg and host port,
1002 * don't need to init otg and host port irq separately.
1003 */
1004 if (rphy->irq > 0)
1005 return 0;
1006
1007 switch (rport->port_id) {
1008 case USB2PHY_PORT_HOST:
1009 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1010 if (rport->ls_irq < 0) {
1011 dev_err(rphy->dev, "no linestate irq provided\n");
1012 return rport->ls_irq;
1013 }
1014
1015 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1016 rockchip_usb2phy_linestate_irq,
1017 IRQF_ONESHOT,
1018 "rockchip_usb2phy", rport);
1019 if (ret) {
1020 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1021 return ret;
1022 }
1023 break;
1024 case USB2PHY_PORT_OTG:
1025 /*
1026 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1027 * interrupts muxed together, so probe the otg-mux interrupt first,
1028 * if not found, then look for the regular interrupts one by one.
1029 */
1030 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1031 if (rport->otg_mux_irq > 0) {
1032 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1033 NULL,
1034 rockchip_usb2phy_otg_mux_irq,
1035 IRQF_ONESHOT,
1036 "rockchip_usb2phy_otg",
1037 rport);
1038 if (ret) {
1039 dev_err(rphy->dev,
1040 "failed to request otg-mux irq handle\n");
1041 return ret;
1042 }
1043 } else {
1044 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1045 if (rport->bvalid_irq < 0) {
1046 dev_err(rphy->dev, "no vbus valid irq provided\n");
1047 ret = rport->bvalid_irq;
1048 return ret;
1049 }
1050
1051 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1052 NULL,
1053 rockchip_usb2phy_bvalid_irq,
1054 IRQF_ONESHOT,
1055 "rockchip_usb2phy_bvalid",
1056 rport);
1057 if (ret) {
1058 dev_err(rphy->dev,
1059 "failed to request otg-bvalid irq handle\n");
1060 return ret;
1061 }
1062
1063 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1064 if (rport->id_irq < 0) {
1065 dev_err(rphy->dev, "no otg-id irq provided\n");
1066 ret = rport->id_irq;
1067 return ret;
1068 }
1069
1070 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq,
1071 NULL,
1072 rockchip_usb2phy_id_irq,
1073 IRQF_ONESHOT,
1074 "rockchip_usb2phy_id",
1075 rport);
1076 if (ret) {
1077 dev_err(rphy->dev,
1078 "failed to request otg-id irq handle\n");
1079 return ret;
1080 }
1081 }
1082 break;
1083 default:
1084 return -EINVAL;
1085 }
1086
1087 return 0;
1088 }
1089
rockchip_usb2phy_host_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1090 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1091 struct rockchip_usb2phy_port *rport,
1092 struct device_node *child_np)
1093 {
1094 int ret;
1095
1096 rport->port_id = USB2PHY_PORT_HOST;
1097 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1098 rport->suspended = true;
1099
1100 mutex_init(&rport->mutex);
1101 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1102
1103 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1104 if (ret) {
1105 dev_err(rphy->dev, "failed to setup host irq\n");
1106 return ret;
1107 }
1108
1109 return 0;
1110 }
1111
rockchip_otg_event(struct notifier_block * nb,unsigned long event,void * ptr)1112 static int rockchip_otg_event(struct notifier_block *nb,
1113 unsigned long event, void *ptr)
1114 {
1115 struct rockchip_usb2phy_port *rport =
1116 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1117
1118 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1119
1120 return NOTIFY_DONE;
1121 }
1122
rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1123 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1124 struct rockchip_usb2phy_port *rport,
1125 struct device_node *child_np)
1126 {
1127 int ret, id;
1128
1129 rport->port_id = USB2PHY_PORT_OTG;
1130 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1131 rport->state = OTG_STATE_UNDEFINED;
1132
1133 /*
1134 * set suspended flag to true, but actually don't
1135 * put phy in suspend mode, it aims to enable usb
1136 * phy and clock in power_on() called by usb controller
1137 * driver during probe.
1138 */
1139 rport->suspended = true;
1140 rport->vbus_attached = false;
1141
1142 mutex_init(&rport->mutex);
1143
1144 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1145 if (rport->mode == USB_DR_MODE_HOST ||
1146 rport->mode == USB_DR_MODE_UNKNOWN) {
1147 ret = 0;
1148 goto out;
1149 }
1150
1151 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1152 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1153
1154 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1155 if (ret) {
1156 dev_err(rphy->dev, "failed to init irq for host port\n");
1157 goto out;
1158 }
1159
1160 if (!IS_ERR(rphy->edev)) {
1161 rport->event_nb.notifier_call = rockchip_otg_event;
1162
1163 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1164 EXTCON_USB_HOST, &rport->event_nb);
1165 if (ret) {
1166 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1167 goto out;
1168 }
1169
1170 if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
1171 /* do initial sync of usb state */
1172 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1173 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
1174 }
1175 }
1176
1177 out:
1178 return ret;
1179 }
1180
rockchip_usb2phy_probe(struct platform_device * pdev)1181 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1182 {
1183 struct device *dev = &pdev->dev;
1184 struct device_node *np = dev->of_node;
1185 struct device_node *child_np;
1186 struct phy_provider *provider;
1187 struct rockchip_usb2phy *rphy;
1188 const struct rockchip_usb2phy_cfg *phy_cfgs;
1189 const struct of_device_id *match;
1190 unsigned int reg;
1191 int index, ret;
1192
1193 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1194 if (!rphy)
1195 return -ENOMEM;
1196
1197 match = of_match_device(dev->driver->of_match_table, dev);
1198 if (!match || !match->data) {
1199 dev_err(dev, "phy configs are not assigned!\n");
1200 return -EINVAL;
1201 }
1202
1203 if (!dev->parent || !dev->parent->of_node) {
1204 rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
1205 if (IS_ERR(rphy->grf)) {
1206 dev_err(dev, "failed to locate usbgrf\n");
1207 return PTR_ERR(rphy->grf);
1208 }
1209 }
1210
1211 else {
1212 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1213 if (IS_ERR(rphy->grf))
1214 return PTR_ERR(rphy->grf);
1215 }
1216
1217 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1218 rphy->usbgrf =
1219 syscon_regmap_lookup_by_phandle(dev->of_node,
1220 "rockchip,usbgrf");
1221 if (IS_ERR(rphy->usbgrf))
1222 return PTR_ERR(rphy->usbgrf);
1223 } else {
1224 rphy->usbgrf = NULL;
1225 }
1226
1227 if (of_property_read_u32_index(np, "reg", 0, ®)) {
1228 dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1229 np);
1230 return -EINVAL;
1231 }
1232
1233 /* support address_cells=2 */
1234 if (reg == 0) {
1235 if (of_property_read_u32_index(np, "reg", 1, ®)) {
1236 dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1237 np);
1238 return -EINVAL;
1239 }
1240 }
1241
1242 rphy->dev = dev;
1243 phy_cfgs = match->data;
1244 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1245 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1246 rphy->irq = platform_get_irq_optional(pdev, 0);
1247 platform_set_drvdata(pdev, rphy);
1248
1249 ret = rockchip_usb2phy_extcon_register(rphy);
1250 if (ret)
1251 return ret;
1252
1253 /* find out a proper config which can be matched with dt. */
1254 index = 0;
1255 while (phy_cfgs[index].reg) {
1256 if (phy_cfgs[index].reg == reg) {
1257 rphy->phy_cfg = &phy_cfgs[index];
1258 break;
1259 }
1260
1261 ++index;
1262 }
1263
1264 if (!rphy->phy_cfg) {
1265 dev_err(dev, "no phy-config can be matched with %pOFn node\n",
1266 np);
1267 return -EINVAL;
1268 }
1269
1270 rphy->clk = of_clk_get_by_name(np, "phyclk");
1271 if (!IS_ERR(rphy->clk)) {
1272 clk_prepare_enable(rphy->clk);
1273 } else {
1274 dev_info(&pdev->dev, "no phyclk specified\n");
1275 rphy->clk = NULL;
1276 }
1277
1278 ret = rockchip_usb2phy_clk480m_register(rphy);
1279 if (ret) {
1280 dev_err(dev, "failed to register 480m output clock\n");
1281 goto disable_clks;
1282 }
1283
1284 index = 0;
1285 for_each_available_child_of_node(np, child_np) {
1286 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1287 struct phy *phy;
1288
1289 /* This driver aims to support both otg-port and host-port */
1290 if (!of_node_name_eq(child_np, "host-port") &&
1291 !of_node_name_eq(child_np, "otg-port"))
1292 goto next_child;
1293
1294 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1295 if (IS_ERR(phy)) {
1296 dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
1297 ret = PTR_ERR(phy);
1298 goto put_child;
1299 }
1300
1301 rport->phy = phy;
1302 phy_set_drvdata(rport->phy, rport);
1303
1304 /* initialize otg/host port separately */
1305 if (of_node_name_eq(child_np, "host-port")) {
1306 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1307 child_np);
1308 if (ret)
1309 goto put_child;
1310 } else {
1311 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1312 child_np);
1313 if (ret)
1314 goto put_child;
1315 }
1316
1317 next_child:
1318 /* to prevent out of boundary */
1319 if (++index >= rphy->phy_cfg->num_ports) {
1320 of_node_put(child_np);
1321 break;
1322 }
1323 }
1324
1325 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1326
1327 if (rphy->irq > 0) {
1328 ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
1329 rockchip_usb2phy_irq,
1330 IRQF_ONESHOT,
1331 "rockchip_usb2phy",
1332 rphy);
1333 if (ret) {
1334 dev_err(rphy->dev,
1335 "failed to request usb2phy irq handle\n");
1336 goto put_child;
1337 }
1338 }
1339
1340 return PTR_ERR_OR_ZERO(provider);
1341
1342 put_child:
1343 of_node_put(child_np);
1344 disable_clks:
1345 if (rphy->clk) {
1346 clk_disable_unprepare(rphy->clk);
1347 clk_put(rphy->clk);
1348 }
1349 return ret;
1350 }
1351
1352 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1353 {
1354 .reg = 0x760,
1355 .num_ports = 2,
1356 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1357 .port_cfgs = {
1358 [USB2PHY_PORT_OTG] = {
1359 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
1360 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1361 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1362 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1363 .id_det_en = { 0x0680, 6, 5, 0, 3 },
1364 .id_det_st = { 0x0690, 6, 5, 0, 3 },
1365 .id_det_clr = { 0x06a0, 6, 5, 0, 3 },
1366 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1367 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1368 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1369 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1370 .utmi_id = { 0x0480, 1, 1, 0, 1 },
1371 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1372 },
1373 [USB2PHY_PORT_HOST] = {
1374 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
1375 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1376 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1377 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1378 }
1379 },
1380 .chg_det = {
1381 .opmode = { 0x0760, 3, 0, 5, 1 },
1382 .cp_det = { 0x0884, 4, 4, 0, 1 },
1383 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1384 .dp_det = { 0x0884, 5, 5, 0, 1 },
1385 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1386 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1387 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1388 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1389 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1390 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1391 },
1392 },
1393 {
1394 .reg = 0x800,
1395 .num_ports = 2,
1396 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1397 .port_cfgs = {
1398 [USB2PHY_PORT_OTG] = {
1399 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
1400 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1401 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1402 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1403 },
1404 [USB2PHY_PORT_HOST] = {
1405 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
1406 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1407 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1408 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1409 }
1410 },
1411 },
1412 { /* sentinel */ }
1413 };
1414
1415 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1416 {
1417 .reg = 0x100,
1418 .num_ports = 2,
1419 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1420 .port_cfgs = {
1421 [USB2PHY_PORT_OTG] = {
1422 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1423 .bvalid_det_en = { 0x3020, 3, 2, 0, 3 },
1424 .bvalid_det_st = { 0x3024, 3, 2, 0, 3 },
1425 .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
1426 .id_det_en = { 0x3020, 5, 4, 0, 3 },
1427 .id_det_st = { 0x3024, 5, 4, 0, 3 },
1428 .id_det_clr = { 0x3028, 5, 4, 0, 3 },
1429 .ls_det_en = { 0x3020, 0, 0, 0, 1 },
1430 .ls_det_st = { 0x3024, 0, 0, 0, 1 },
1431 .ls_det_clr = { 0x3028, 0, 0, 0, 1 },
1432 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1433 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1434 .utmi_id = { 0x0120, 6, 6, 0, 1 },
1435 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1436 },
1437 [USB2PHY_PORT_HOST] = {
1438 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 },
1439 .ls_det_en = { 0x3020, 1, 1, 0, 1 },
1440 .ls_det_st = { 0x3024, 1, 1, 0, 1 },
1441 .ls_det_clr = { 0x3028, 1, 1, 0, 1 },
1442 .utmi_ls = { 0x0120, 17, 16, 0, 1 },
1443 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
1444 }
1445 },
1446 .chg_det = {
1447 .opmode = { 0x0100, 3, 0, 5, 1 },
1448 .cp_det = { 0x0120, 24, 24, 0, 1 },
1449 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1450 .dp_det = { 0x0120, 25, 25, 0, 1 },
1451 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1452 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1453 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1454 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1455 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1456 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1457 },
1458 },
1459 { /* sentinel */ }
1460 };
1461
1462 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1463 {
1464 .reg = 0x100,
1465 .num_ports = 2,
1466 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1467 .port_cfgs = {
1468 [USB2PHY_PORT_OTG] = {
1469 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1470 .bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
1471 .bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
1472 .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
1473 .id_det_en = { 0x0110, 5, 4, 0, 3 },
1474 .id_det_st = { 0x0114, 5, 4, 0, 3 },
1475 .id_det_clr = { 0x0118, 5, 4, 0, 3 },
1476 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1477 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1478 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1479 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1480 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1481 .utmi_id = { 0x0120, 6, 6, 0, 1 },
1482 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1483 },
1484 [USB2PHY_PORT_HOST] = {
1485 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
1486 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1487 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1488 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1489 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1490 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1491 }
1492 },
1493 .chg_det = {
1494 .opmode = { 0x0100, 3, 0, 5, 1 },
1495 .cp_det = { 0x0120, 24, 24, 0, 1 },
1496 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1497 .dp_det = { 0x0120, 25, 25, 0, 1 },
1498 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1499 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1500 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1501 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1502 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1503 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1504 },
1505 },
1506 { /* sentinel */ }
1507 };
1508
1509 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1510 {
1511 .reg = 0x700,
1512 .num_ports = 2,
1513 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1514 .port_cfgs = {
1515 [USB2PHY_PORT_HOST] = {
1516 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1517 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1518 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1519 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1520 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1521 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1522 }
1523 },
1524 },
1525 { /* sentinel */ }
1526 };
1527
1528 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1529 {
1530 .reg = 0xe450,
1531 .num_ports = 2,
1532 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1533 .port_cfgs = {
1534 [USB2PHY_PORT_OTG] = {
1535 .phy_sus = { 0xe454, 1, 0, 2, 1 },
1536 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1537 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1538 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1539 .id_det_en = { 0xe3c0, 5, 4, 0, 3 },
1540 .id_det_st = { 0xe3e0, 5, 4, 0, 3 },
1541 .id_det_clr = { 0xe3d0, 5, 4, 0, 3 },
1542 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1543 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1544 .utmi_id = { 0xe2ac, 8, 8, 0, 1 },
1545 },
1546 [USB2PHY_PORT_HOST] = {
1547 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1548 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1549 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1550 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1551 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1552 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1553 }
1554 },
1555 .chg_det = {
1556 .opmode = { 0xe454, 3, 0, 5, 1 },
1557 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1558 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1559 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1560 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1561 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1562 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1563 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1564 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1565 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1566 },
1567 },
1568 {
1569 .reg = 0xe460,
1570 .num_ports = 2,
1571 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1572 .port_cfgs = {
1573 [USB2PHY_PORT_OTG] = {
1574 .phy_sus = { 0xe464, 1, 0, 2, 1 },
1575 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1576 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1577 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1578 .id_det_en = { 0xe3c0, 10, 9, 0, 3 },
1579 .id_det_st = { 0xe3e0, 10, 9, 0, 3 },
1580 .id_det_clr = { 0xe3d0, 10, 9, 0, 3 },
1581 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1582 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1583 .utmi_id = { 0xe2ac, 11, 11, 0, 1 },
1584 },
1585 [USB2PHY_PORT_HOST] = {
1586 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1587 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1588 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1589 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1590 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1591 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1592 }
1593 },
1594 },
1595 { /* sentinel */ }
1596 };
1597
1598 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1599 {
1600 .reg = 0xfe8a0000,
1601 .num_ports = 2,
1602 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1603 .port_cfgs = {
1604 [USB2PHY_PORT_OTG] = {
1605 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
1606 .bvalid_det_en = { 0x0080, 3, 2, 0, 3 },
1607 .bvalid_det_st = { 0x0084, 3, 2, 0, 3 },
1608 .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
1609 .id_det_en = { 0x0080, 5, 4, 0, 3 },
1610 .id_det_st = { 0x0084, 5, 4, 0, 3 },
1611 .id_det_clr = { 0x0088, 5, 4, 0, 3 },
1612 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
1613 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
1614 .utmi_id = { 0x00c0, 6, 6, 0, 1 },
1615 },
1616 [USB2PHY_PORT_HOST] = {
1617 /* Select suspend control from controller */
1618 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
1619 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1620 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1621 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1622 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1623 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1624 }
1625 },
1626 .chg_det = {
1627 .opmode = { 0x0000, 3, 0, 5, 1 },
1628 .cp_det = { 0x00c0, 24, 24, 0, 1 },
1629 .dcp_det = { 0x00c0, 23, 23, 0, 1 },
1630 .dp_det = { 0x00c0, 25, 25, 0, 1 },
1631 .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
1632 .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
1633 .idp_src_en = { 0x0008, 9, 9, 0, 1 },
1634 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
1635 .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
1636 .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
1637 },
1638 },
1639 {
1640 .reg = 0xfe8b0000,
1641 .num_ports = 2,
1642 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1643 .port_cfgs = {
1644 [USB2PHY_PORT_OTG] = {
1645 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1646 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1647 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1648 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1649 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
1650 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
1651 },
1652 [USB2PHY_PORT_HOST] = {
1653 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1654 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1655 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1656 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1657 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1658 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1659 }
1660 },
1661 },
1662 { /* sentinel */ }
1663 };
1664
1665 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1666 {
1667 .reg = 0x100,
1668 .num_ports = 2,
1669 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1670 .port_cfgs = {
1671 [USB2PHY_PORT_OTG] = {
1672 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1673 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1674 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1675 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1676 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1677 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1678 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1679 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
1680 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
1681 },
1682 [USB2PHY_PORT_HOST] = {
1683 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 },
1684 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1685 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1686 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1687 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
1688 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
1689 }
1690 },
1691 .chg_det = {
1692 .opmode = { 0x0100, 3, 0, 5, 1 },
1693 .cp_det = { 0x0804, 1, 1, 0, 1 },
1694 .dcp_det = { 0x0804, 0, 0, 0, 1 },
1695 .dp_det = { 0x0804, 2, 2, 0, 1 },
1696 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1697 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1698 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1699 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1700 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1701 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1702 },
1703 },
1704 { /* sentinel */ }
1705 };
1706
1707 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1708 { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
1709 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1710 { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
1711 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1712 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1713 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1714 { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
1715 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
1716 {}
1717 };
1718 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1719
1720 static struct platform_driver rockchip_usb2phy_driver = {
1721 .probe = rockchip_usb2phy_probe,
1722 .driver = {
1723 .name = "rockchip-usb2phy",
1724 .of_match_table = rockchip_usb2phy_dt_match,
1725 },
1726 };
1727 module_platform_driver(rockchip_usb2phy_driver);
1728
1729 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1730 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1731 MODULE_LICENSE("GPL v2");
1732
