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Searched refs:reset_domain (Results 1 – 19 of 19) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_reset.c110 struct amdgpu_reset_domain *reset_domain = container_of(ref, in amdgpu_reset_destroy_reset_domain() local
113 if (reset_domain->wq) in amdgpu_reset_destroy_reset_domain()
114 destroy_workqueue(reset_domain->wq); in amdgpu_reset_destroy_reset_domain()
116 kvfree(reset_domain); in amdgpu_reset_destroy_reset_domain()
122 struct amdgpu_reset_domain *reset_domain; in amdgpu_reset_create_reset_domain() local
124 reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL); in amdgpu_reset_create_reset_domain()
125 if (!reset_domain) { in amdgpu_reset_create_reset_domain()
130 reset_domain->type = type; in amdgpu_reset_create_reset_domain()
131 kref_init(&reset_domain->refcount); in amdgpu_reset_create_reset_domain()
133 reset_domain->wq = create_singlethread_workqueue(wq_name); in amdgpu_reset_create_reset_domain()
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Dmxgpu_ai.c262 if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0) in xgpu_ai_mailbox_flr_work()
265 down_write(&adev->reset_domain->sem); in xgpu_ai_mailbox_flr_work()
280 atomic_set(&adev->reset_domain->in_gpu_reset, 0); in xgpu_ai_mailbox_flr_work()
281 up_write(&adev->reset_domain->sem); in xgpu_ai_mailbox_flr_work()
321 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain, in xgpu_ai_mailbox_rcv_irq()
Dmxgpu_nv.c286 if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0) in xgpu_nv_mailbox_flr_work()
289 down_write(&adev->reset_domain->sem); in xgpu_nv_mailbox_flr_work()
304 atomic_set(&adev->reset_domain->in_gpu_reset, 0); in xgpu_nv_mailbox_flr_work()
305 up_write(&adev->reset_domain->sem); in xgpu_nv_mailbox_flr_work()
351 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain, in xgpu_nv_mailbox_rcv_irq()
Damdgpu_reset.h125 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
127 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
Damdgpu_xgmi.c220 amdgpu_reset_put_reset_domain(hive->reset_domain); in amdgpu_xgmi_hive_release()
221 hive->reset_domain = NULL; in amdgpu_xgmi_hive_release()
406 if (adev->reset_domain->type != XGMI_HIVE) { in amdgpu_get_xgmi_hive()
407 hive->reset_domain = in amdgpu_get_xgmi_hive()
409 if (!hive->reset_domain) { in amdgpu_get_xgmi_hive()
418 amdgpu_reset_get_reset_domain(adev->reset_domain); in amdgpu_get_xgmi_hive()
419 hive->reset_domain = adev->reset_domain; in amdgpu_get_xgmi_hive()
Damdgpu_ras_eeprom.c208 down_read(&adev->reset_domain->sem); in __write_table_header()
213 up_read(&adev->reset_domain->sem); in __write_table_header()
410 down_read(&adev->reset_domain->sem); in __amdgpu_ras_eeprom_write()
416 up_read(&adev->reset_domain->sem); in __amdgpu_ras_eeprom_write()
578 down_read(&adev->reset_domain->sem); in amdgpu_ras_eeprom_update_header()
583 up_read(&adev->reset_domain->sem); in amdgpu_ras_eeprom_update_header()
673 down_read(&adev->reset_domain->sem); in __amdgpu_ras_eeprom_read()
679 up_read(&adev->reset_domain->sem); in __amdgpu_ras_eeprom_read()
Damdgpu_xgmi.h45 struct amdgpu_reset_domain *reset_domain; member
Damdgpu_device.c427 if (down_read_trylock(&adev->reset_domain->sem)) in amdgpu_device_skip_hw_access()
428 up_read(&adev->reset_domain->sem); in amdgpu_device_skip_hw_access()
430 lockdep_assert_held(&adev->reset_domain->sem); in amdgpu_device_skip_hw_access()
456 down_read_trylock(&adev->reset_domain->sem)) { in amdgpu_device_rreg()
458 up_read(&adev->reset_domain->sem); in amdgpu_device_rreg()
541 down_read_trylock(&adev->reset_domain->sem)) { in amdgpu_device_wreg()
543 up_read(&adev->reset_domain->sem); in amdgpu_device_wreg()
2324 timeout, adev->reset_domain->wq, in amdgpu_device_init_schedulers()
2465 if (!hive->reset_domain || in amdgpu_device_ip_init()
2466 !amdgpu_reset_get_reset_domain(hive->reset_domain)) { in amdgpu_device_ip_init()
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Damdgpu_debugfs.c1484 r = down_write_killable(&adev->reset_domain->sem); in amdgpu_debugfs_test_ib_show()
1513 up_write(&adev->reset_domain->sem); in amdgpu_debugfs_test_ib_show()
1743 r = down_read_killable(&adev->reset_domain->sem); in amdgpu_debugfs_ib_preempt()
1786 up_read(&adev->reset_domain->sem); in amdgpu_debugfs_ib_preempt()
1849 ret = down_read_killable(&adev->reset_domain->sem); in amdgpu_reset_dump_register_list_read()
1855 up_read(&adev->reset_domain->sem); in amdgpu_reset_dump_register_list_read()
1860 ret = down_read_killable(&adev->reset_domain->sem); in amdgpu_reset_dump_register_list_read()
1865 up_read(&adev->reset_domain->sem); in amdgpu_reset_dump_register_list_read()
1907 ret = down_write_killable(&adev->reset_domain->sem); in amdgpu_reset_dump_register_list_write()
1914 up_write(&adev->reset_domain->sem); in amdgpu_reset_dump_register_list_write()
Dgmc_v9_0.c792 down_read_trylock(&adev->reset_domain->sem)) { in gmc_v9_0_flush_gpu_tlb()
798 up_read(&adev->reset_domain->sem); in gmc_v9_0_flush_gpu_tlb()
906 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { in gmc_v9_0_flush_gpu_tlb_pasid()
933 up_read(&adev->reset_domain->sem); in gmc_v9_0_flush_gpu_tlb_pasid()
942 up_read(&adev->reset_domain->sem); in gmc_v9_0_flush_gpu_tlb_pasid()
945 up_read(&adev->reset_domain->sem); in gmc_v9_0_flush_gpu_tlb_pasid()
Damdgpu_fence.c826 if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work)) in gpu_recover_get()
829 *val = atomic_read(&adev->reset_domain->reset_res); in gpu_recover_get()
Dmxgpu_vi.c564 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain, in xgpu_vi_mailbox_rcv_irq()
Dgmc_v10_0.c336 down_read_trylock(&adev->reset_domain->sem)) { in gmc_v10_0_flush_gpu_tlb()
346 up_read(&adev->reset_domain->sem); in gmc_v10_0_flush_gpu_tlb()
Damdgpu_amdkfd.c271 amdgpu_reset_domain_schedule(adev->reset_domain, in amdgpu_amdkfd_gpu_reset()
Damdgpu.h1046 struct amdgpu_reset_domain *reset_domain; member
Damdgpu_ras.c2978 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); in amdgpu_ras_reset_gpu()
/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_engine_cs.c388 u32 reset_domain; in get_reset_domain() local
421 reset_domain = engine_reset_domains[id]; in get_reset_domain()
432 reset_domain = engine_reset_domains[id]; in get_reset_domain()
435 return reset_domain; in get_reset_domain()
473 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915), in intel_engine_setup()
Dintel_engine_types.h355 u32 reset_domain; member
Dintel_reset.c317 hw_mask |= engine->reset_domain; in __gen6_reset_engines()
518 reset_mask |= engine->reset_domain; in __gen11_reset_engines()