Home
last modified time | relevance | path

Searched refs:reg_off (Results 1 – 25 of 60) sorted by relevance

123

/Linux-v6.1/drivers/mmc/host/
Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
[all …]
/Linux-v6.1/drivers/pinctrl/sunplus/
Dsppctl.c112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_reg_and_bit_offset() argument
117 *reg_off = (offset / 32) * 4; in sppctl_get_reg_and_bit_offset()
123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_moon_reg_and_bit_offset() argument
133 *reg_off = (offset / 16) * 4; in sppctl_get_moon_reg_and_bit_offset()
139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) in sppctl_prep_moon_reg_and_offset() argument
143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); in sppctl_prep_moon_reg_and_offset()
227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, in sppctl_gmx_set() argument
240 writel(reg, pctl->moon1_base + reg_off * 4); in sppctl_gmx_set()
264 u32 reg_off, bit_off, reg; in sppctl_first_get() local
266 bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off); in sppctl_first_get()
[all …]
/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_vbif.c59 u32 reg_off; in dpu_hw_set_mem_type() local
74 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1; in dpu_hw_set_mem_type()
76 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0; in dpu_hw_set_mem_type()
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
90 u32 reg_off; in dpu_hw_set_limit_conf() local
94 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf()
96 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf()
98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf()
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
[all …]
Ddpu_hw_catalog.c386 .reg_off = 0x2AC, .bit_off = 0},
388 .reg_off = 0x2B4, .bit_off = 0},
390 .reg_off = 0x2BC, .bit_off = 0},
392 .reg_off = 0x2C4, .bit_off = 0},
394 .reg_off = 0x2AC, .bit_off = 8},
396 .reg_off = 0x2B4, .bit_off = 8},
398 .reg_off = 0x2C4, .bit_off = 8},
400 .reg_off = 0x2C4, .bit_off = 12},
402 .reg_off = 0x3A8, .bit_off = 15},
404 .reg_off = 0x3B0, .bit_off = 15},
[all …]
Ddpu_hw_top.c95 u32 reg_off, bit_off; in dpu_hw_setup_clk_force_ctrl() local
107 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; in dpu_hw_setup_clk_force_ctrl()
110 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_setup_clk_force_ctrl()
117 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
/Linux-v6.1/tools/lib/bpf/
Dusdt.c208 short reg_off; member
1188 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg64) in calc_pt_regs_off() macro
1190 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg32) in calc_pt_regs_off()
1192 { {"rip", "eip", "", ""}, reg_off(rip, eip) }, in calc_pt_regs_off()
1193 { {"rax", "eax", "ax", "al"}, reg_off(rax, eax) }, in calc_pt_regs_off()
1194 { {"rbx", "ebx", "bx", "bl"}, reg_off(rbx, ebx) }, in calc_pt_regs_off()
1195 { {"rcx", "ecx", "cx", "cl"}, reg_off(rcx, ecx) }, in calc_pt_regs_off()
1196 { {"rdx", "edx", "dx", "dl"}, reg_off(rdx, edx) }, in calc_pt_regs_off()
1197 { {"rsi", "esi", "si", "sil"}, reg_off(rsi, esi) }, in calc_pt_regs_off()
1198 { {"rdi", "edi", "di", "dil"}, reg_off(rdi, edi) }, in calc_pt_regs_off()
[all …]
/Linux-v6.1/drivers/pinctrl/
Dpinctrl-digicolor.c129 int bit_off, reg_off; in dc_set_mux() local
132 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
134 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
137 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
147 int bit_off, reg_off; in dc_pmx_request_gpio() local
150 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
152 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
170 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
176 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
178 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
[all …]
/Linux-v6.1/drivers/irqchip/
Dirq-davinci-aintc.c82 unsigned int irq_off, reg_off, prio, shift; in davinci_aintc_init() local
125 for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG; in davinci_aintc_init()
126 reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) { in davinci_aintc_init()
129 davinci_aintc_writel(prio, reg_off); in davinci_aintc_init()
156 for (irq_off = 0, reg_off = 0; in davinci_aintc_init()
158 irq_off += 32, reg_off += 0x04) in davinci_aintc_init()
159 davinci_aintc_setup_gc(davinci_aintc_base + reg_off, in davinci_aintc_init()
/Linux-v6.1/drivers/clk/meson/
Daxg.c29 .reg_off = HHI_MPLL_CNTL,
34 .reg_off = HHI_MPLL_CNTL,
39 .reg_off = HHI_MPLL_CNTL,
44 .reg_off = HHI_MPLL_CNTL2,
49 .reg_off = HHI_MPLL_CNTL,
54 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_SYS_PLL_CNTL,
98 .reg_off = HHI_SYS_PLL_CNTL,
103 .reg_off = HHI_SYS_PLL_CNTL,
108 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
Dg12a-aoclk.c122 .reg_off = AO_RTC_ALT_CLK_CNTL0,
127 .reg_off = AO_RTC_ALT_CLK_CNTL0,
132 .reg_off = AO_RTC_ALT_CLK_CNTL1,
137 .reg_off = AO_RTC_ALT_CLK_CNTL1,
142 .reg_off = AO_RTC_ALT_CLK_CNTL0,
213 .reg_off = AO_CEC_CLK_CNTL_REG0,
218 .reg_off = AO_CEC_CLK_CNTL_REG0,
223 .reg_off = AO_CEC_CLK_CNTL_REG1,
228 .reg_off = AO_CEC_CLK_CNTL_REG1,
233 .reg_off = AO_CEC_CLK_CNTL_REG0,
Dgxbb.c89 .reg_off = HHI_MPLL_CNTL,
94 .reg_off = HHI_MPLL_CNTL,
99 .reg_off = HHI_MPLL_CNTL,
104 .reg_off = HHI_MPLL_CNTL2,
109 .reg_off = HHI_MPLL_CNTL,
114 .reg_off = HHI_MPLL_CNTL,
166 .reg_off = HHI_HDMI_PLL_CNTL,
171 .reg_off = HHI_HDMI_PLL_CNTL,
176 .reg_off = HHI_HDMI_PLL_CNTL,
181 .reg_off = HHI_HDMI_PLL_CNTL2,
[all …]
Dparm.h25 u16 reg_off; member
34 regmap_read(map, p->reg_off, &val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
Dgxbb-aoclk.c89 .reg_off = AO_RTC_ALT_CLK_CNTL0,
94 .reg_off = AO_RTC_ALT_CLK_CNTL0,
99 .reg_off = AO_RTC_ALT_CLK_CNTL1,
104 .reg_off = AO_RTC_ALT_CLK_CNTL1,
109 .reg_off = AO_RTC_ALT_CLK_CNTL0,
Dg12a.c33 .reg_off = HHI_FIX_PLL_CNTL0,
38 .reg_off = HHI_FIX_PLL_CNTL0,
43 .reg_off = HHI_FIX_PLL_CNTL0,
48 .reg_off = HHI_FIX_PLL_CNTL1,
53 .reg_off = HHI_FIX_PLL_CNTL0,
58 .reg_off = HHI_FIX_PLL_CNTL0,
102 .reg_off = HHI_SYS_PLL_CNTL0,
107 .reg_off = HHI_SYS_PLL_CNTL0,
112 .reg_off = HHI_SYS_PLL_CNTL0,
117 .reg_off = HHI_SYS_PLL_CNTL0,
[all …]
Daxg-aoclk.c103 .reg_off = AO_RTC_ALT_CLK_CNTL0,
108 .reg_off = AO_RTC_ALT_CLK_CNTL0,
113 .reg_off = AO_RTC_ALT_CLK_CNTL1,
118 .reg_off = AO_RTC_ALT_CLK_CNTL1,
123 .reg_off = AO_RTC_ALT_CLK_CNTL0,
Dmeson8b.c58 .reg_off = HHI_MPLL_CNTL,
63 .reg_off = HHI_MPLL_CNTL,
68 .reg_off = HHI_MPLL_CNTL,
73 .reg_off = HHI_MPLL_CNTL2,
78 .reg_off = HHI_MPLL_CNTL,
83 .reg_off = HHI_MPLL_CNTL,
174 .reg_off = HHI_VID_PLL_CNTL,
179 .reg_off = HHI_VID_PLL_CNTL,
184 .reg_off = HHI_VID_PLL_CNTL,
189 .reg_off = HHI_VID_PLL_CNTL2,
[all …]
/Linux-v6.1/sound/soc/tegra/
Dtegra210_mbdrc.c787 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_hw_params() local
790 reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL, in tegra210_mbdrc_hw_params()
791 reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, in tegra210_mbdrc_hw_params()
849 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_component_init() local
852 reg_off + TEGRA210_MBDRC_IIR_CFG, in tegra210_mbdrc_component_init()
858 reg_off + TEGRA210_MBDRC_IN_ATTACK, in tegra210_mbdrc_component_init()
864 reg_off + TEGRA210_MBDRC_IN_RELEASE, in tegra210_mbdrc_component_init()
870 reg_off + TEGRA210_MBDRC_FAST_ATTACK, in tegra210_mbdrc_component_init()
889 reg_off + TEGRA210_MBDRC_IN_THRESHOLD, in tegra210_mbdrc_component_init()
906 reg_off + TEGRA210_MBDRC_OUT_THRESHOLD, in tegra210_mbdrc_component_init()
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/octeon_ep/
Doctep_main.h287 #define octep_write_csr(octep_dev, reg_off, value) \ argument
288 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
290 #define octep_write_csr64(octep_dev, reg_off, val64) \ argument
291 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
293 #define octep_read_csr(octep_dev, reg_off) \ argument
294 readl((octep_dev)->mmio[0].hw_addr + (reg_off))
296 #define octep_read_csr64(octep_dev, reg_off) \ argument
297 readq((octep_dev)->mmio[0].hw_addr + (reg_off))
/Linux-v6.1/drivers/thermal/samsung/
Dexynos_tmu.c452 unsigned int reg_off, j; in exynos5433_tmu_set_trip_temp() local
456 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; in exynos5433_tmu_set_trip_temp()
459 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; in exynos5433_tmu_set_trip_temp()
463 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_temp()
466 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_temp()
472 unsigned int reg_off, j; in exynos5433_tmu_set_trip_hyst() local
476 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; in exynos5433_tmu_set_trip_hyst()
479 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; in exynos5433_tmu_set_trip_hyst()
483 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
486 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
[all …]
/Linux-v6.1/drivers/net/ethernet/cavium/liquidio/
Docteon_device.h740 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
741 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
743 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
744 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
746 #define octeon_read_csr(oct_dev, reg_off) \ argument
747 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
749 #define octeon_read_csr64(oct_dev, reg_off) \ argument
750 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
/Linux-v6.1/drivers/pinctrl/spear/
Dpinctrl-plgpio.c85 u32 reg_off = REG_OFFSET(0, reg, pin); in is_plgpio_set() local
88 regmap_read(regmap, reg_off, &val); in is_plgpio_set()
96 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_set() local
100 regmap_update_bits(regmap, reg_off, mask, mask); in plgpio_reg_set()
106 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_reset() local
110 regmap_update_bits(regmap, reg_off, mask, 0); in plgpio_reg_reset()
330 u32 reg_off; in plgpio_irq_set_type() local
347 reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); in plgpio_irq_set_type()
348 regmap_read(plgpio->regmap, reg_off, &val); in plgpio_irq_set_type()
352 regmap_write(plgpio->regmap, reg_off, val | (1 << offset)); in plgpio_irq_set_type()
[all …]
/Linux-v6.1/drivers/misc/habanalabs/goya/
Dgoya.c1086 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); in goya_init_dma_qman() local
1099 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); in goya_init_dma_qman()
1100 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); in goya_init_dma_qman()
1102 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); in goya_init_dma_qman()
1103 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
1104 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
1106 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); in goya_init_dma_qman()
1107 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); in goya_init_dma_qman()
1108 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); in goya_init_dma_qman()
1109 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); in goya_init_dma_qman()
[all …]
/Linux-v6.1/arch/x86/kvm/
Dlapic.h170 static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off) in __kvm_lapic_get_reg() argument
172 return *((u32 *) (regs + reg_off)); in __kvm_lapic_get_reg()
175 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument
177 return __kvm_lapic_get_reg(apic->regs, reg_off); in kvm_lapic_get_reg()
/Linux-v6.1/drivers/mtd/nand/raw/
Dqcom_nandc.c910 int reg_off, const void *vaddr, in prep_bam_dma_desc_cmd() argument
924 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
930 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
996 int reg_off, const void *vaddr, int size, in prep_adm_dma_desc() argument
1034 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
1042 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
1158 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1164 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1176 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1182 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
[all …]

123