Home
last modified time | relevance | path

Searched refs:reg_block (Results 1 – 10 of 10) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dppatomctrl.c49 ATOM_INIT_REG_BLOCK *reg_block, in atomctrl_retrieve_ac_timing() argument
55 ((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize)); in atomctrl_retrieve_ac_timing()
84 ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ; in atomctrl_retrieve_ac_timing()
102 ATOM_INIT_REG_BLOCK *reg_block, in atomctrl_set_mc_reg_address_table() argument
106 uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize)) in atomctrl_set_mc_reg_address_table()
108 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0]; in atomctrl_set_mc_reg_address_table()
138 ATOM_INIT_REG_BLOCK *reg_block; in atomctrl_initialize_mc_reg_table() local
156 reg_block = (ATOM_INIT_REG_BLOCK *) in atomctrl_initialize_mc_reg_table()
158 result = atomctrl_set_mc_reg_address_table(reg_block, table); in atomctrl_initialize_mc_reg_table()
163 reg_block, table); in atomctrl_initialize_mc_reg_table()
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c2876 u32 reg_block, lb_interrupt_mask; in dce_v8_0_set_crtc_vblank_interrupt_state() local
2885 reg_block = CRTC0_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
2888 reg_block = CRTC1_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
2891 reg_block = CRTC2_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
2894 reg_block = CRTC3_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
2897 reg_block = CRTC4_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
2900 reg_block = CRTC5_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()
2909 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
2911 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
2914 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
[all …]
Datom.h140 uint16_t reg_block; member
Datom.c194 idx += gctx->reg_block; in atom_get_src_int()
261 val = gctx->reg_block; in atom_get_src_int()
466 idx += gctx->reg_block; in atom_put_dst()
528 gctx->reg_block = val; in atom_put_dst()
918 ctx->ctx->reg_block = U16(*ptr); in atom_op_setregblock()
920 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); in atom_op_setregblock()
1276 ctx->reg_block = 0; in amdgpu_atom_execute_table()
Ddce_v6_0.c2827 u32 reg_block, interrupt_mask; in dce_v6_0_set_crtc_vblank_interrupt_state() local
2836 reg_block = SI_CRTC0_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2839 reg_block = SI_CRTC1_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2842 reg_block = SI_CRTC2_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2845 reg_block = SI_CRTC3_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2848 reg_block = SI_CRTC4_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2851 reg_block = SI_CRTC5_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
2860 interrupt_mask = RREG32(mmINT_MASK + reg_block); in dce_v6_0_set_crtc_vblank_interrupt_state()
2862 WREG32(mmINT_MASK + reg_block, interrupt_mask); in dce_v6_0_set_crtc_vblank_interrupt_state()
2865 interrupt_mask = RREG32(mmINT_MASK + reg_block); in dce_v6_0_set_crtc_vblank_interrupt_state()
[all …]
Damdgpu_atombios.c1441 ATOM_INIT_REG_BLOCK *reg_block = in amdgpu_atombios_init_mc_reg_table() local
1446 ((u8 *)reg_block + (2 * sizeof(u16)) + in amdgpu_atombios_init_mc_reg_table()
1447 le16_to_cpu(reg_block->usRegIndexTblSize)); in amdgpu_atombios_init_mc_reg_table()
1448 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0]; in amdgpu_atombios_init_mc_reg_table()
1449 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / in amdgpu_atombios_init_mc_reg_table()
1486 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in amdgpu_atombios_init_mc_reg_table()
/Linux-v6.1/drivers/gpu/drm/radeon/
Datom.c196 idx += gctx->reg_block; in atom_get_src_int()
263 val = gctx->reg_block; in atom_get_src_int()
468 idx += gctx->reg_block; in atom_put_dst()
530 gctx->reg_block = val; in atom_put_dst()
884 ctx->ctx->reg_block = U16(*ptr); in atom_op_setregblock()
886 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); in atom_op_setregblock()
1227 ctx->reg_block = 0; in atom_execute_table_scratch_unlocked()
Datom.h137 uint16_t reg_block; member
Dradeon_atombios.c4001 ATOM_INIT_REG_BLOCK *reg_block = in radeon_atom_init_mc_reg_table() local
4006 ((u8 *)reg_block + (2 * sizeof(u16)) + in radeon_atom_init_mc_reg_table()
4007 le16_to_cpu(reg_block->usRegIndexTblSize)); in radeon_atom_init_mc_reg_table()
4008 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0]; in radeon_atom_init_mc_reg_table()
4009 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / in radeon_atom_init_mc_reg_table()
4046 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in radeon_atom_init_mc_reg_table()
/Linux-v6.1/drivers/net/ethernet/intel/i40e/
Di40e_common.c947 u32 reg_block = 0; in i40e_pre_tx_queue_cfg() local
951 reg_block = abs_queue_idx / 128; in i40e_pre_tx_queue_cfg()
955 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
964 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); in i40e_pre_tx_queue_cfg()
1267 u32 reg_block = 0; in i40e_clear_hw() local
1270 reg_block = abs_queue_idx / 128; in i40e_clear_hw()
1274 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_clear_hw()
1279 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); in i40e_clear_hw()