Home
last modified time | relevance | path

Searched refs:regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_0_3_offset.h709 #define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX … macro
Dgc_11_0_0_offset.h703 #define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX … macro