Home
last modified time | relevance | path

Searched refs:regPWRSEQ1_BL_PWM_CNTL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_3_1_4_offset.h7203 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
Ddpcs_4_2_3_offset.h125 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
Ddpcs_4_2_2_offset.h108 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
Ddpcs_4_2_0_offset.h121 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_4_offset.h11569 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
Ddcn_3_1_5_offset.h12321 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
Ddcn_3_1_2_offset.h12456 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
Ddcn_3_1_6_offset.h13052 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro