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Searched refs:regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_4_offset.h11787 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_3_1_5_offset.h12523 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_3_1_2_offset.h12658 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_3_2_0_offset.h11858 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_3_2_1_offset.h11867 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro
Ddcn_3_1_6_offset.h13254 #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX … macro